Xilinx LogiCORE 1000BASE-X - Figure 7-7: Clock Management - Multiple Core Instances, Virtex-5 Rocketio Gtp

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 91
UG155 March 24, 2008
Clock Sharing Across Multiple Cores with RocketIO
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Figure 7-7: Clock Management - Multiple Core Instances, Virtex-5 RocketIO GTP
Transceivers for 1000BASE-X
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
userclk
userclk2
Virtex-5
GTP
RocketIO
(0)
CLKIN
rocketio_wrapper_gtp_tile
Virtex-5
GTP
RocketIO
(1)
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
userclk
userclk2
userclk2
(125 MHz)
BUFG
TXUSRCLK0
TXUSRCLK20
RXUSRCLK0
RXUSRCLK20
TXUSRCLK1
TXUSRCLK21
RXUSRCLK1
RXUSRCLK21
clkin
(125MHz)
REFCLKOUT
component_name_block
(Block Level)
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
userclk
userclk2
Virtex-5
GTP
RocketIO
(0)
Virtex-5
GTP
RocketIO
(1)
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
userclk
userclk2
TXUSRCLK0
TXUSRCLK20
RXUSRCLK0
RXUSRCLK20
TXUSRCLK1
TXUSRCLK21
RXUSRCLK1
RXUSRCLK21
REFCLKOUT
component_name_block
(Block Level)
NC
IBUFGDS
IPAD
brefclkp
IPAD
brefclkn
CLKIN
rocketio_wrapper_gtp_tile
rocketio_wrapper_gtp
rocketio_wrapper_gtp