Xilinx LogiCORE 1000BASE-X - Figure 8-10: Clock Management with Multiple Core Instances with Virtex-5 Gtx

114 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
Chapter 8: SGMII / Dynamic Standards Switching with RocketIO Transceivers
R
.
Figure 8-10: Clock Management with Multiple Core Instances with Virtex-5 GTX
RocketIO Transceivers for SGMII
component_name_block
(Block Level)
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
userclk
userclk2
Virtex-5
GTP
RocketIO
(0)
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
userclk
userclk2
TXUSRCLK0
TXUSRCLK20
RXUSRCLK0
RXUSRCLK20
REFCLKOUT
RXRECCLK0
FPGA
fabric
Rx
Elastic
Buffer
BUFR
Virtex-5
GTP
RocketIO
(1)
TXUSRCLK1
TXUSRCLK21
RXUSRCLK1
RXUSRCLK21
RXRECCLK1
FPGA
fabric
Rx
Elastic
Buffer
BUFR
component_name_block
(Block Level)
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
userclk
userclk2
Virtex-5
GTP
RocketIO
(0)
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
userclk
userclk2
userclk2
(125 MHz)
TXUSRCLK0
TXUSRCLK20
RXUSRCLK0
RXUSRCLK20
REFCLKOUT
RXRECCLK0
FPGA
fabric
Rx
Elastic
Buffer
BUFR
Virtex-5
GTP
RocketIO
(1)
CLKIN
TXUSRCLK1
TXUSRCLK21
RXUSRCLK1
RXUSRCLK21
RXRECCLK1
FPGA
fabric
Rx
Elastic
Buffer
BUFR
clkin
(125MHz)
IBUFGDS
IPAD
brefclkp
IPAD
brefclkn
CLKIN
NC
rocketio_wrapper_gtp_tile
rocketio_wrapper_gtp_tile
rocketio_wrapper_gtp
rocketio_wrapper_gtp
userclk2 (125MHz)
DCM
CLKIN
CLK0
FB
BUFG
CLKDV
BUFG
userclk (62.5MHz)