Xilinx LogiCORE 1000BASE-X - Figure 6-2: Ten-Bit-Interface Receiver Logic

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 71
UG155 March 24, 2008
Ten-Bit-Interface Logic
R
synchronous to pma_rx_clk0_bufg and pma_rx_clk1_bufg, respectively. These
busses are then immediately registered inside the core on their respective clock.
Figure 6-2: Ten-Bit-Interface Receiver Logic
component_name _block (Block Level from example design)
pma_rx_clk0
IBUFG
IOB LOGIC
IPAD
rx_code_group[0]
IBUF
IPAD
rx_code_group_ibuf[0]
D
Q
Ethernet 1000BASE-X PCS/PMA
or SGMII LogiCORE
pma_rx_clk0
BUFG
IOB LOGIC
pma_rx_clk0_ibufg
D
Q
pma_rx_clk1
IBUFG
IOB LOGIC
IPAD
BUFG
pma_rx_clk1_ibufg
pma_rx_clk1
rx_code_group0[0]
rx_code_group1[0]
rx_code_group1_reg[0]
rx_code_group0_reg[0]
pma_rx_clk0_bufg
(62.5 MHz)
pma_rx_clk1_bufg
(62.5 MHz)