Xilinx LogiCORE 1000BASE-X - Client Side Interface

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 31
UG155 March 24, 2008
Core Interfaces
R
Figure 2-7 shows the pinout for the Ethernet 1000BASE-X PCS/PMA or SGMII core using
the optional dynamic switching logic (between 1000BASE-X and SGMII standards). This
mode is shown used with a RocketIO transceiver interface. For more information, see
Chapter 11, “Dynamic Switching of 1000BASE-X and SGMII Standards.”
Client Side Interface
GMII Pinout
Table 2-1 describes the GMII-side interface signals of the core common to all
parameterizations of the core. These are typically attached to an Ethernet MAC, either off-
chip or internally integrated. The HDL example design delivered with the core connects
these signals to IOBs to provide a place-and-route example.
For more information, see “Designing with the Client-side GMII for the 1000BASE-X
Standard” in Chapter 5.
Figure 2-7: Component Pinout with the Dynamic Switching Logic
mdc
mdio_in
gmii_rxd[7:0]
gmii_txd[7:0]
gmii_tx_en
mgt_rx_reset
gmii_tx_er
reset
gmii_rx_dv
gmii_rx_er
GMII
MDIO
phyad[4:0]
gtx_clk
signal_detect
mdio_out
mdio_tri
rxbufstatus[1:0]
rxchariscomma
rxcharisk
RocketIO Interface
gmii_isolate
link_timer_basex[8:0]
an_interrupt
Auto_Negotiation
mgt_tx_reset
rxclkcorcnt[2:0]
rxdata[7:0]
rxdisperr
rxnotintable
rxrundisp
txbuferr
userclk
dcm_locked
userclk2
powerdown
txchardispmode
txchardispval
txcharisk
txdata
enablealign
link_timer_sgmii[8:0]
basex_or_sgmii
status_vector[4:0]