Xilinx LogiCORE 1000BASE-X - Page 30

30 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
Chapter 2: Core Architecture
R
Figure 2-6 shows the pinout for the Ethernet 1000BASE-X PCS/PMA or SGMII core when
using a TBI without the optional PCS Management Registers.
Figure 2-6: Component Pinout Using Ten-Bit Interface
without PCS Management Registers
gmii_rxd[7:0]
gmii_txd[7:0]
gmii_tx_en
tx_code_group[9:0]
rx_code_group0[9:0]
gmii_tx_er
reset
gmii_rx_dv
gmii_rx_er
pma_rx_clk0
GMII
gtx_clk
signal_detect
loc_ref
ewrap
pma_rx_clk1
en_cdet
rx_code_group1[9:0]
Ten-Bit Interface (TBI)
gmii_isolate
configuration_vector[3:0]
MDIO Replacement
status_vector[4:0]