Xilinx LogiCORE 1000BASE-X - Figure 8-7: Clock Management with Multiple Core Instances with Virtex-II Pro

108 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
Chapter 8: SGMII / Dynamic Standards Switching with RocketIO Transceivers
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the device. For more information, see the Virtex-II Pro RocketIO Transceiver User Guide. Each
brefclk domain must use its own DCM to derive its version of userclk and userclk2.
Figure 8-7: Clock Management with Multiple Core Instances with Virtex-II Pro
RocketIO Transceivers for SGMII
DCM
CLKIN CLK0
CLK2X180
FB
BUFG
BUFG
IBUFGDS
TXUSRCLK
BREFCLK
TXUSRCLK2
RXUSRCLK
RXUSRCLK2
GT_CUSTOM
brefclk (62.5MHz)
userclk (62.5 MHz)
userclk2
(125 MHz)
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
userclk
userclk2
TXUSRCLK
BREFCLK
TXUSRCLK2
RXUSRCLK
RXUSRCLK2
GT_CUSTOM
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
userclk
userclk2
IPAD
brefclkp
IPAD
brefclkn
FPGA
fabric
Rx
Elastic
Buffer
RXRECCLK
FPGA
fabric
Rx
Elastic
Buffer
RXRECCLK
component_name _block
(Block Level)
component_name _block
(Block Level)
local
clock
routing
local
clock
routing