Xilinx LogiCORE 1000BASE-X - Optional Configuration Vector

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 151
UG155 March 24, 2008
Optional Configuration Vector
R
Register 17: Vendor-specific Standard Selection Register
Optional Configuration Vector
If “MDIO Management Interface” is omitted, relevant configuration signals are brought
out of the core. These signals are bundled into the CONFIGURATION_VECTOR signal as
defined in Table 9-36.
Figure 9-5: Dynamic Switching (Register 17)
Table 9-35: Vendor-specific Register: Standard Selection Register (Register 17)
Bit(s) Name Description Attributes Default Value
17.15:1 Reserved Always return 0s Returns 0s 000000000000000
16.0 Standard 0 = Core will perform the
1000BASE-X standard. Registers 0
to 16 will behave as per
“1000BASE-X Standard Using the
Optional Auto-Negotiation”
1= Core will perform the SGMII
standard. Registers 0 to 16 will
behave as per “SGMII Standard
Using the Optional Auto-
Negotiation”.
read/write Determined by the
basex_or_sgmii
port
15 0
Reg 17
RESERVED
1
BASEX OR SGMII