Xilinx System Generator V2.1 - Page 7

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Gateway Out.........................................................................................................99
Quantization Error Blocks ....................................................................................101
Display .................................................................................................................101
Memory .....................................................................................................................102
Dual Port RAM .....................................................................................................102
FIFO ....................................................................................................................106
ROM ....................................................................................................................107
Single Port RAM ..................................................................................................110
State Machine ...........................................................................................................114
Mealy State Machine ...........................................................................................114
Moore State Machine ..........................................................................................116
Registered Mealy State Machine .........................................................................119
Registered Moore State Machine ........................................................................123
Chapter 4 System Generator Software Features
Using the System Generator installer .......................................................................127
Uninstalling previous System Generator directories ............................................127
Installed System Generator directory ..................................................................128
Using Black Boxes ....................................................................................................128
Example model ....................................................................................................128
Black Box window ................................................................................................129
Use of mixed language projects ...............................................................................130
Incorporating mixed language black boxes .........................................................130
Tips for creating a high performance design ............................................................132
Using the System Generator Constraints Files..........................................................133
System Clock Period ............................................................................................133
Multicycle Path Constraints ..................................................................................133
IOB Timing and Placement Constraints ...............................................................134
Example for showing constraints use...................................................................134
Important Issues...................................................................................................136
Files automatically created by System Generator ....................................................137
Chapter 5 Using the Xilinx Software
Xilinx ISE 4.1i Project Navigator ...............................................................................139
Opening a System Generator project ..................................................................139
Customizing your System Generator project .......................................................139
Implementing your design ...................................................................................140
Simulating using ModelSim within the Project Navigator ....................................141
Using an EDIF software flow ....................................................................................143
Simulation .................................................................................................................143
Compiling your IP ................................................................................................143
Associating ModelSim with ISE 4.1i Project Navigator ........................................144
Xilinx software tools resources .................................................................................145
Chapter 6 Auxiliary Files
Demonstration designs..............................................................................................146
Perl scripts.................................................................................................................147