Xilinx XC4000 Series

September 18, 1996 (Version 1.04) 4-15
G'
4

G
1
• • • G
4
F
1
• • • F
4
C
1
• • • C
4
WRITE
DECODER

1 of 16
D
IN
16-LATCH
ARRAY
X6752
4

4

MUX
F'
WRITE
DECODER

1 of 16
D
IN
16-LATCH
ARRAY
READ
ADDRESS

READ
ADDRESS

WRITE PULSE
LATCH
ENABLE
LATCH
ENABLE
K
(CLOCK)
WE
D
1
D
0
EC
WRITE PULSE
MUX
4

4

Figure 3: 16x2 (or 16x1) Edge-Triggered Single-Port RAM
G'
4

G
1
• • • G
4
F
1
• • • F
4
C
1
• • • C
4
WRITE
DECODER

1 of 16
D
IN
16-LATCH
ARRAY
X6754
4

4

MUX
F'
WRITE
DECODER

1 of 16
D
IN
16-LATCH
ARRAY
READ
ADDRESS

READ
ADDRESS

WRITE PULSE
LATCH
ENABLE
LATCH
ENABLE
K
(CLOCK)
WE
D
1
/A
4
D
0
EC
EC
WRITE PULSE
MUX
4

4

H'
Figure 4: 32x1 Edge-Triggered Single-Port RAM (F and G addresses are identical)