Xilinx XC4000 Series

XC4000 Series Field Programmable Gate Arrays
4-18 September 18, 1996 (Version 1.04)
G'
G
1
• • • G
4
F
1
• • • F
4
WRITE
DECODER

1 of 16
D
IN
16-LATCH
ARRAY
X6748
4

4

MUX
F'
WRITE
DECODER

1 of 16
D
IN
16-LATCH
ARRAY
READ
ADDRESS

READ
ADDRESS

WRITE PULSE
LATCH
ENABLE
LATCH
ENABLE
K
(CLOCK)
WRITE PULSE
MUX
4

4

C
1
• • • C
4
4

WE
D
1
D
0
EC
Figure 7: 16x1 Edge-Triggered Dual-Port RAM