Xilinx XC4000 Series

XC4000 Series Field Programmable Gate Arrays
4-20 September 18, 1996 (Version 1.04)
Enable
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G'
4
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G
1
• • • G
4
F
1
• • • F
4
WRITE
DECODER

1 of 16
D
IN
16-LATCH
ARRAY
X6746
4

READ ADDRESS
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MUX
Enable

F'
WRITE
DECODER

1 of 16
D
IN
16-LATCH
ARRAY
4

READ ADDRESS
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MUX
4
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C
1
• • • C
4
4

WE
D
1
D
0
EC
Figure 9: 16x2 (or 16x1) Level-Sensitive Single-Port RAM
Enable

WRITE
DECODER

1 of 16
D
IN
16-LATCH
ARRAY
X6749
4

READ ADDRESS

MUX
Enable

WRITE
DECODER

1 of 16
D
IN
16-LATCH
ARRAY
4

READ ADDRESS

MUX
G'
4

G
1
• • • G
4
F
1
• • • F
4
C
1
• • • C
4
4

F'
WE
D
1
/A
4
D
0
EC
4

H'
Figure 10: 32x1 Level-Sensitive Single-Port RAM (F and G addresses are identical)