Xilinx XC4000 Series User Manual

XC4000 Series Field Programmable Gate Arrays
4-10 September 18, 1996 (Version 1.04)
Table 3: CLB Count of Selected XC4000-Series Soft Macros
7400 Equivalents CLBs Barrel Shifters CLBs Multiplexers CLBs
‘138
‘139
‘147
‘148
‘150
‘151
‘152
‘153
‘154
‘157
‘158
‘160
‘161
‘162
‘163
‘164
‘165s
‘166
‘168
‘174
‘194
‘195
‘280
‘283
‘298
‘352
‘390
‘518
‘521
5
2
5
6
5
3
3
2
16
2
2
5
6
8
8
4
9
5
7
3
5
3
3
8
2
2
3
3
3
brlshft4
brlshft8
4
13
m2-1e
m4-1e
m8-1e
m16-1e
1
1
3
5
4-Bit Counters
cd4cd
cd4cle
cd4rle
cb4ce
cb4cle
cb4re
3
5
6
3
6
5
Registers
rd4r
rd8r
rd16r
2
4
8
8- and 16-Bit Counters Shift Registers
cb8ce
cb8re
cc16ce
cc16cle
cc16cled
6
10
9
9
21
sr8ce
sr16re
4
8
Decoders
d2-4e
d3-8e
d4-16e
2
4
16
Identity Comparators
comp4
comp8
comp16
1
2
5
Explanation of counter nomenclature
cb = binary counter
cd = BCD counter
cc = cascadable binary counter
d = bidirectional
l = loadable
e = clock enable
r = synchronous reset
c = asynchronous clear
Magnitude Comparators
compm4
compm8
compm16
4
9
20
Explanation of RAM nomenclature
s = single-port edge-triggered
d = dual-port edge-triggered
no extension = level-sensitive
RAMs
ram16x4
ram16x4s
ram16x4d
2
2
4

Xilinx XC4000 Series Specifications

General

Brand	Xilinx
Model	XC4000 Series
Category	Controller
Language	English