Yamaha DX21 - BASIC CIRCUIT OPERATIONS

DX21
DX21
■ BASIC CIRCUIT OPERATIONS
1. The Main Clock Circuit
The clock generation circuit for the CPU and soud
generation, generates a signal having a frequency of
7.15909MHz. The signal of 7.15090MHz is applied
to the EXTAL pin of the CPU, and divided by a
factor of 4 inside the CPU to create the system
clock.
A signal having a frequency of 3.58MHz is used for
sound generation.
2. The Sub-Clock Circuit
This clock circuit generates a signal of 500kHz for
A/D conversion and the MIDI clock. The 500kHz
clock signals are applied to pin 22 of the CPU,
which in turn is divided by a factor of 16 inside the
CPU to create the 31.25kHz MIDI clock.
3. The Reset Circuit
A reset signal is generated an RC network and
Schmitt Trigger invertor 1C. A reset 1C is used to
short any remaining voltage of the 10 microfarad
charging capacitor to ground on power-up. Then
the reset 1C goes to a high impedance state to
allow the capacitor to charge via a resistor con¬
nected to the +5V supply. Therefore, initially
the reset signal is a logic "LOW" level until the
capacitor reaches the threshold of the Schmitt
Trigger Invertor ICs and then the reset signal
switches to a "HIGH" logic level. The reset signal
is also fed to two transistors. One transistor controls
the Battery Back-Up circuit and the other control
the CHIP SELECT 2 signal for the RAM ICs.
The CHIP SELECT 2 or CE2 signals disables the
RAM ICs so they will not be selected. This
eliminates the possibility of the RAM ICs being
accessed and accidentally written to.
4. The CPU, ROM and RAM
• The CPU with clock input of 7.15909MHz,
operates with a system clock of approximately
1.8MHz. The access time for the ROM, RAM,
and other components connected to the bus
must be faster as the read/write pulse width is
approximately 260nS.
• The ROM is allocated from addresses $8000 to
$FFFF of the memory, with $8000 to $A480
being the area for the 128 voice data, and $A480
to $FFFD being the program area. The use of
two 128K bytes ROM is possible. In this case,
jumper *1 is moved to *2, and IC36 is installed.
• The RAM is allocated from addresses $1000 to
$27 FF of the memory with the area from
$1000 to $ 191F used as the voice memory
area, and the area from $1920 and above is
used for the various stacks and registers.
Furthermore, the entire area is memory backed
up by a battery to enable the memory to be
retained after the power is turned off.
5. The Address Map
The CPU addresses are as follows:
$00 $1F
Internal CPU registers and
ports
$20
A/D output port
$22 A/D start
$24 OPM
$26 LCD
$28,$29
CHORU5 ON-OFF
$40 ~ $FF RAM in CPU
$1000 ~$27EF RAM
$8000~$FFFF ROM
6. The A/D Circuit
The A/D circuit uses an 8 bit 8 channel ADC 1C.
Five of the eight input channels are used. When
a channel number and start pulse are received from
CPU, conversion is performed for that channel.
The CPU is notified of the completed conversion
when it receives the EOC signal from the ADC 1C.
The CPU outputs the OE signal after detection of
EOC, and data is fetched from the data bus.
7. The Sound Generation Circuit
This circuit consists of 4 function operator with
8 note capability. The FM tone generator or
operator and the DAC, generate the FM tones
based on data from the CPU. There are two
channels for audio output, and different voices
are possible on each channel.
8. The Chorus Circuit
This is a phase modulation circuit with a 128 stage
BBD. The effect is turned on/off by the CPU.
9. The HP Circuit
This is an amplification circuit for the headphones
which allows use of headphones having an im¬
pedance of 8 to 150 ohms.
10. The Switch Scan Circuit
The switch scan circuit is connected directly to
the CPU and is capable of scanning 128 (8 x 16)
switches. With the DX21, 61 Keyboard switches
and 42 panel switches are scanned, for a total of
103 switches.
11. The MIDI circuit
The MIDI circuit is connected directly to the CPU
and has IN, OUT, and THRU OUT terminals, and
meets MIDI standards VI. 0.
12. The Cassette Interface Circuit
The cassette interface circuit connected is also
directly to the CPU and runs the cassette I/O
at a rate of 1200 baud which is controlled by the
CPU software.
5