Zte ZXSDR BS8800 - Power Distribution

Chapter 2 Working Principle
F IGURE 12 C LOCK S IGNAL F LOW
The CC clock in Figure 12 takes GPS system as reference. The
clock reference can be GPS output clock reference, the upper-level
clock of Abis E1/T1 synchronization, or the BITS reference clock
input by CC front panel. Its selection depends on the specific ap-
plications.
Power Distribution
-48V Power
Distribution
ZXSDR BS8800 supports -48V/+24V power supply. This sec- tion
describes -48V and +24V power distribution principles.
With the adoption of -48V DC power supply, the —48V power dis-
tribution subrack implements the overall equipment power distri-
bution. After being led into the cabinet, the primary power is dis-
tributed to the baseband subrack (BBU), RF subrack (composed
of multiple RSUs) and fan subrack (FAN) by the power distribu-
tion subrack (PDM). The PDM provides 9 circuit breakers to control
power-on and power-off of the baseband subrack, fan subrack and
every RSU.
Figure 13 illustrates —48V power distribution.
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