ABB REG650 - Page 54

Table 54. Configurable logic blocks
Logic block Quantity
with cycle
time
Range or value Accuracy
5 ms 20 ms 100 ms
AND 60 60 160 - -
OR 60 60 160 - -
XOR 10 10 20 - -
INVERTER 30 30 80 - -
SRMEMORY 10 10 20 - -
RSMEMORY 10 10 20 - -
GATE 10 10 20 - -
PULSETIMER 10 10 20 (0.000–90000.000) s ± 0.5% ± 25 ms for 20
ms cycle time
TIMERSET 10 10 20 (0.000–90000.000) s ± 0.5% ± 25 ms for 20
ms cycle time
LOOPDELAY 10 10 20
Table 55. Configurable logic Q/T
Logic block
Quantity
with cycle
time
Range or value Accuracy
20 ms 100 ms
ANDQT 20 100 - -
ORQT 20 100 - -
XORQT 10 30 - -
INVERTERQT 20 100 - -
RSMEMORYQT 10 30 - -
SRMEMORYQT 15 10 - -
PULSETIMERQT 10 30 (0.000–
90000.000) s
± 0.5% ± 25 ms for 20 ms cycle time
TIMERSETQT 10 30 (0.000–
90000.000) s
± 0.5% ± 25 ms for 20 ms cycle time
INVALIDQT 6 6 - -
INDCOMBSPQT 10 10 - -
INDEXTSPQT 10 10 - -
Table 56. Elapsed time integrator with limit transgression and overflow supervision TEIGGIO
Function
Cycle time (ms) Range or value Accuracy
Elapsed time integration 5 0 ~ 999999.9 s ±0.05% or ±0.01 s
20 0 ~ 999999.9 s ±0.05% or ±0.04 s
100 0 ~ 999999.9 s ±0.05% or ±0.2 s
Generator protection REG650
1MRK 502 050-BEN B
Product version: 1.3
54 ABB