The Acqiris SA220P is a high-performance 14-bit ADC card designed for signal acquisition, offering advanced real-time processing capabilities for embedded OEM applications in various measurement, imaging, and processing systems. It is a dual-channel device capable of capturing waveforms from DC up to 1.2 GHz.
Function Description:
The SA220P features two 14-bit DC-coupled channels with sampling rates up to 2 GS/s. It incorporates a powerful Xilinx Kintex UltraScale FPGA, enabling real-time signal processing such as waveform averaging or peak listing. The PCIe Gen 3 interface facilitates high data transfer rates and streaming capabilities to the host computer at up to 6.5 GB/s. The card is designed with a proprietary low noise front-end, offering excellent signal fidelity and high signal-to-noise ratio (SNR). Its optimized response allows for precise sub-hundred-picosecond pulse analysis.
The card supports various acquisition modes and optional functions for real-time signal processing in the FPGA. These include:
- Digitizer acquisition mode (DGT): For single or multi-record acquisitions (up to 131,072 records).
- Real-time averaging mode (AVG option): Reduces random noise and improves signal-to-noise ratio. It supports single-channel and dual-channel real-time sampling and averaging at 2 GS/s, with up to 65,536 triggers in steps of 1 trigger. Effective acquisition length is up to 512k samples per channel or 1M samples when using only one channel. Noise suppression accumulation (NSA) and self-trigger mode for minimal synchronous (pattern) noise are also available.
- Simultaneous acquisition and readout (CST option): Allows continuous streaming of records, enabling longer acquisition durations and reducing trigger loss.
- Averager with simultaneous acquisition and readout (AVG & CST): Combines averaging and streaming for minimal dead time between accumulations and sustained high data rates without trigger loss.
Other signal processing features include:
- Baseline stabilization and digital offset: Recommended for time-domain applications requiring stable baselines, such as pulse sequences. It estimates and corrects baseline fluctuations from low-frequency noise or measurement side-effects. A configurable digital offset can be applied after stabilization.
- Sampling rate reduction (binary decimation): Programmable binary decimation can lower the sample rate, available in both digitizer and averager modes. Decimation ratios of 2, 4, and 8 are supported, yielding sampling rates of 1 GS/s, 500 MS/s, and 250 MS/s, respectively.
- Data inversion: Enables inversion of channel data, useful for processing negative pulses with baseline stabilization or thresholding.
- Thresholding (Zero-Suppress - ZS1 option): A data reduction mode that selects data above a user-defined threshold, suppressing data below it. This feature compresses data and is available in digitizer mode, optionally combined with streaming (CST). It supports hysteresis to define when samples below the threshold are ignored.
Important Technical Specifications:
- Channels: 2
- Resolution: 14-bit
- Sampling Rate: 1 GS/s or 2 GS/s (default)
- Bandwidth: DC to 1.2 GHz (typical for 2 GS/s), DC to 475 MHz (typical for 1 GS/s version with LSR/LBW options)
- Memory: 4 GB (MEA option) or 8 GB (MEB option)
- Input Impedance: 50 Ω
- Input Coupling: DC
- Full Scale Ranges (FSR): 500 mV (max operating voltage ±600 mVpk) and 2.5 V (max operating voltage ±3 Vpk)
- Trigger Sources: Internal (input channel), External (TRG IN), Software, Self-Trigger
- External Reference (REF IN): 10 MHz or 100 MHz, -3 dBm to +3 dBm signal level, 50 Ω impedance, AC coupling, 440 mVpp (sinus) minimum amplitude, 2 mW maximum power, 900 mVpp (sinus) maximum voltage.
- Trigger Output (TRG OUT): LVTTL 3.3V, 50 Ω source, ±15 mA maximum output current capability.
- Multi-purpose I/O (IO 1, 2, 3): 3.3 V CMOS compatible (5V Tolerant buffer), configurable as inputs (In-AccumulationEnable, In-TriggerEnable, In-BScanSync, In-CScanSync) or outputs (Out-LowLevel, Out-HighLevel, Out-AScanSync, Out-AScanEna, Out-AScanUp, Out-BScanSync, Out-CScanSync).
- PCIe Interface: Gen 3 x8, up to 6.5 GB/s data transfer rate.
Usage Features:
- Driver Initialization: The AqMD3 IVI driver (IVI-C and IVI.NET) provides access to the card's functionality. Initialization involves calling
AqMD3_InitWithOptions to establish an I/O connection or set up simulation mode.
- Attribute Access: Attributes are accessed via IVI-defined accessor functions (e.g.,
GetAttributeViInt32, SetAttributeViInt32) using unique attribute IDs.
- Configuration: The card's configuration (e.g., channel settings, trigger, sampling rate) is initially set to pre-defined default values. Changes to properties/attributes are not applied immediately to hardware; an explicit
ApplySetup call is required. Some methods like SelfTest, SelfCalibrate, Initiate, Read, and Reset perform an implicit ApplySetup.
- Calibration: A self-calibration is mandatory for accurate measurements and is performed for the current configuration state. A new calibration is needed after any configuration change. The
SelfCalibrate function performs a fast calibration. The driver includes a "smart calibration" feature that stores calibration information, reducing the need for re-calibration if acquisition parameters remain the same.
- Triggering: Supports internal, external, software, and self-trigger modes. Pre- and post-trigger delays can be applied, though pre-trigger is not supported in Averager mode or with baseline stabilization, zero suppress, data inversion, or CST.
- Time-stamps: The card features a time-stamp counter for precise trigger arrival times, essential for multi-record acquisitions.
- Bandwidth Limiter: The ADC supports several bandwidth filters at different frequencies (20 MHz, 200 MHz, 700 MHz). Users can enable or bypass the bandwidth limiter and select the desired filter frequency.
- Binary Decimation: To perform binary decimation, the sampling rate attribute (
AQMD3_ATTR_SAMPLE_RATE for IVI-C or SampleRate for IVI.NET) should be set to a lower value.
- Software Trigger: Software triggers can be generated using
AqMD3_SendSoftwareTrigger (IVI-C) or IAqMD3Trigger.SendSoftwareTrigger (IVI.NET).
Maintenance Features:
- Cleaning Precautions: Disconnect the card from mains before cleaning. Use a dry cloth or one slightly dampened with water for external parts. Avoid internal cleaning. Use alcohol in a well-ventilated area for connectors, ensuring it evaporates before re-energizing.
- Firmware Updates: The
AqMD3Verify utility checks the control FPGA firmware version and can propose updates using the Firmware Update Utility. After a successful update, the computer must be powered off and restarted for the update to take effect.
- Internal Temperature Management: The card's fan speed is automatically controlled to maintain the FPGA core temperature below 100°C. The DPU FPGA core temperature can be monitored via
BoardTemperature (IVI.NET) or AqMD3_QueryBoardTemperature (IVI-C).
- Hibernation Mode: Hibernation while the ADC card is in operation is not supported. It is recommended to close the ADC card before the host computer enters hibernation. If the system manages hibernation, the application should close the card and re-initialize it upon waking. A self-calibration is required after powering on the card.
- Safety Notes: Adhere to safety precautions, including ensuring proper grounding, inspecting cables, and avoiding contact with live circuits. Do not exceed maximum signal levels. The card contains no operator-serviceable parts; all replacements must be done by Acqiris.
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