ADLINK Technology SMARC LEC-MTK-I1200 - Page 24

LEC-MTK-i1200 User’s Guide SGET SMARC Rev 2.1
Page 24 copyright © 2023 ADLINK Technology Inc.
4.3.1.1 DSI0 mode
Name
Pin
#
Description
I/O
Name
Pin #
Description
DSI0_D0+
DSI0_D0-
DSI0_D1+
DSI0_D1-
DSI0_D2+
DSI0_D2-
DSI0_D3+
DSI0_D3-
S125
S126
S128
S129
S131
S132
S137
S138
Primary DSI panel differential pair data lines
O
D-PHY
Runtime
No blocking capacitors or termination required. Layout for 90
Ohms differential impedance.
DSI0_CLK+
DSI0_CLK-
S134
S135
Primary DSI panel differential pair clock
lines
O
D-PHY
Runtime
LCD0_VDD_EN
S133
Primary panel power enable
O
CMOS
1.8V
Runtime
Active high
LCD0_BKLT_EN
S127
Primary panel backlight enable
O
CMOS
1.8V
Runtime
Active high
LCD0_BKLT_PWM
S141
Primary panel brightness control through
pulse width modulation (PWM)
O
CMOS
1.8V
Runtime
Through pulse width modulation (PWM)
DSI0_TE
S144
Primary DSI panel tearing effect signal
I
CMOS
1.8V
Runtime
1M PD
I2C_LCD_DAT
S140
DDC data line used for flat panel detection
and control
I/O OD
CMOS
1.8V
Runtime
PU 2k2
I2C_LCD_CK
S139
DDC clock line used for flat panel detection
and control
O OD
CMOS
1.8V
Runtime
PU 2k2
DSI1_D0+
DSI1_D0-
DSI1_D1+
DSI1_D1-
DSI1_D2+
DSI1_D2-
DSI1_D3+
DSI1_D3-
S111
S112
S114
S115
S117
S118
S120
S121
Secondary DSI differential pair data lines
O LVDS
D-PHY
Runtime
Not supported
DSI1_CLK+
DSI1_CLK-
S108
S109
Secondary DSI differential pair clock lines.
O LVDS
D-PHY
Runtime
Not supported
LCD1_VDD_EN
S116
Secondary panel power enable, active high
O
CMOS
1.8V
Runtime
Not supported
LCD1_BKLT_EN
S107
Secondary panel backlight enable, active
high
O
CMOS
1.8V
Runtime
Not supported