2-9 System Micro-Computer
The system micro-computer decodes and executes all
instructions, and controls all data transfers. It consists of a
microprocessor, an address decoder, RAM and ROM
memories, data buffers/latches, and a real time clock as
shown in Figure 2-3.
2-10 Microprocessor and Clock Circuits. These circuits
contain a high performance 8-bit microprocessor(U201) and
associated clock circuits. The microprocessor operates on a 1
MHz cycle, which it derives from a 4 MHz ceramic resonator
oscillator(Y201). The 1 MHz Q signal is generated by the
microprocessor for use by other circuit.
A 4 millisecond (approximately) clock signal, applied to the
microprocessor interrupt input, enables the microprocessor
to keep track of real time. This allows the microprocessor to
form necessary tasks on a regular basis. The real time clock
signal is also used to keep track of the time that has elapsed
since the output was last changed. This enables
microprocessor to determine if a CV/CC mode change
occurred before the selected time delay (see Reprogramming
Delay discussion in Section V of the Operating Manual). The
microprocessor inhibits the OCP function until the delay is
over.
The microprocessor also uses the 4 millisecond clock to
determine when to refresh the front panel display and to
perform other regularly scheduled jobs.
The R/W (read/write) output from the microprocessor
indicates the direction of flow on the data bus, either to or
from the microprocessor. A low level R/W signal indicates
that the microprocessor is writing data onto the data bus. A
high level R/W signal indicates that the microprocessor is
reading data that was placed on the bus by the addressed
circuit. The microprocessor uses the address decoder circuit
and the address bus to specify the data transfer locations.
Addresses are valid on the rising edge of the Q signal.
2-11 Data Bus latches (U217) and Buffers (U216). The
timing sequence of the microprocessor is such that the
circuits providing data for the microprocessor are de-
selected (address disappears) before the microprocessor can
read the data. The data bus latches (U217) latch the data to
be read by the microprocessor. The data is updated on every
falling Q pulse. Data put on the data bus by the
microprocessor goes around the latches though buffers
(U216).
2-12 Free-Run and Signature Analysis Jumpers. The data
bus is connected to the microprocessor through a jumper
pack (W202). For some signature analysis tests of the
microprocessor kernel (microprocessor, RAM, ROM), the
data bus is broken by moving W202 from the NORMAL
position to the NOP position (see paragraph 4-23). This
connects a NOP (no operation) code (free run) to the
microprocessor data inputs. The NOP code does not contain
an address for the next instruction so the microprocessor
goes to the next highest address. Therefore, the address bus
looks like a 16-bit counter that continuously rolls over and
starts at zero. The contents of each address appear
sequentially on the data bus (other side of the break) In
addition, for all signature analysis tests, jumper W201
must be moved from the NORM RUN position to the SIG
ANALYSIS position (see paragraph 4-23).
2-13 Address Bus and Address Decoder. The
microprocessor has 16 address lines (A0-A15) allowing it to
address 65,536 locations. The address decoder (U208) allows
each addressable circuit to look at a shorter address. The
chip select signals (CS0-CS8) are decoded from the higher
order address lines (A12-A15). When a data buffer’s CS is
decoded, it places its data on the data bus lines. When a data
latch’s CS is decoded, the output of each latch will be set to
the logic state that is present on the associated data bus line.
If the chip select for the RAM (random access memory),
ROM (read only memory), or talker/listener chip is
decoded, the selected circuit will decode the lower order
address bits supplied to it on the address bus.
2-14 Memory (ROM and RAM). The system microcomputer
contains both ROM (U206) and RAM (U207) devices. The
32KK non-volatile ROM contains the operating program and
parameters. The 2 K static RAM stores variables voltage to
be programmed, output current readback, etc. A third
memory chip, shown in the output board interface block of
Figure 2-3, is the EEPROM (electrically erasable
programmable memory). The EEPROM (U230) stores all of
the system constants including calibration constants, the
supply’s GPIB address, and model number (see paragraph
2-19).
2-15 Real Time Clock. The real time clock (U209) consists
of a 14-stage ripple counter that divides the 1 MHz Q clock
signal from the microprocessor to produce a pulse every 4
milliseconds. The real-time clock is used by the
microprocessor to schedule regular jobs as described
previously. The TIMER ENABLE signal resets the counter to
zero.
2-16 Output Boards Interface
2-17 Data Buffers. These 3-state buffers (U212) place the
serial data from each output board and the EEPROM on the
supply’s system microcomputer data bus lines when chip
select CS3 is decoded. Serial data from output boards 1-4
appears on data bus lines D0-D3, respectively, and EEPROM
2-4
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This circuit provides the interface between the system
microcomputer and each of the output boards (up to 4) in
the power supply. Data is transferred serially one bit at a
time between latches/buffers on the GPIB board and
optoisolators on the output boards. As shown in Figure 2-3,
the latches/buffers use data bus lines D0-D3 to send/receive
data from the applicable output. Data line D0 is used for
output board 1, D1 for output board 2, D2 for output board
3 (if present), and D3 for output board 4 (if present). A
controlled and regulated 5 volt line is also generated on the
GPIB board to operate art of the opto-isolators on the
output boards. In addition to interfacing with the output
boards, the latches/buffers interface with the 4 K bit serial
EEPROM in which system constants are stored.
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