The OV signals is also sent to the analog multiplexer so that
it can be measured during power on self test.
2-31 Readback Amplifier and Analog Multiplexer. The
analog multiplexer (U323) selects one of eight inputs (value
of these inputs are from 0 to 10 Volts) to be applied to the
readback signal comparator (U324) for the A-to-D converter.
The selected signal is determined by address lines (A0-A2)
which are received from the microcomputer. The analog
inputs to the multiplexer indicate the following:
COM - hardwired to common to reduce noise when no
signals are being sampled.
FUSE - output board’s return fuse status (read back
during power-on self test)
VFS - Readback amp output (U315A)
V/I MUX - Range amp output (U315C)
CV DAC - voltage DAC output
CC DAC - current DAC output
OV DAC - overvoltage DAC output
U315C can be configured as an inverting or non-inverting
amplifier. Swiches (U365) determine it’s configuration as
well as the input to amplify. U366 is use to determine the
gain of the amplifier.
U315B is used as a buffer. For current readback, inputs from
the 4 terminal shunt resistor R408 are select via U365. For
voltage readback low range, U366 (D) is used as the input to
U315C.
2-32 Readback DAC and Signal Comparator. The
readback DAC (U321), amplifier (U362), readback signal
comparator (U324), and analog multiplexer (U323) along
with the microcomputer (U312) form an analog-to-digital
converter (ADC) which monitors the output board signals
sent to the analog multiplexer.
The readback DAC (U321) and amplifier U362 convert the
digital input signal from the microcomputer to an analog
signal in the range of 0 to – 10 volts. The DAC internally
formulates the 14-bit DAC data from the 8-bit (DB0-DB7)
data bus (same as the CV DAC described above).
The output of the DAC and the output of the analog
multiplexer are applied to the signal comarator U324. The
readback DAC, under the control of the microcomputer,
successively approximates the value of the multiplexer’s
output to a 14-bit resolution,. Starting from the most
significant bit, each bit is successively compare to the
multiplexer’s output and is kept or discarded depending on
whether its value is less than (kept) or greater than
(discarded) the multiplexer’s output.
Each comparison (successive approximation) is evaluated by
the microprocessor via its INT input. The microcomputer
maintains a running total of the approximations (sum of the
kept bits) which, when complete, represents the value of the
analog multiplexer’s output.
2-33 CV and CC Programming Range Switching. U367,
U364, and resistor pack U381 determine the attenuation
factor for the CV and CC signals. Programming range
latchU367 receives information via the data bus (DO0 and
DO1), which determines if the power supply will operate in
the low or high voltage and current ranges. Using this
information, U367 sets analog switches U364 for the proper
divider tap for the desired range (full DAC output O to – 10
V for high range, or a portion of the 10 V for the low range).
2-34 Readback Range Switching. U365, U366, and U368
provide readback of the output of the power supply to the
analog multiplexer (U323), except for the 50 V range (VFS).
Readback latch U368 receives information via data lines
DO0 and DO1 which set up monitor switches U365 and gain
select switches U366 to readback the output parameters.
2-35 Signal Processor. This special purpose IC (U327)
processes both analog and digital signals to interface the
microcomputer with the power mesh and control circuits.
The circuits can be functionally divided into status monitor,
overvoltage detector and driver, and power-on/start-up
circuits.
Status Monitor
– this circuit consists of comparators to monitor
the control loops, logic to decode these input line, and flip-
flops to catch and hold changes. The inputs to the status
comparators are the CV LOOP, + CL LOOP, and – CL LOOP
signals from the power control circuits (see Figure 2-5). The
outputs of the comparators are combined in logic circuits
which then go into the set inputs of flip-flops which hold the
status of CVO, + CLO, - CLO, and UNREG outputs. UNREG
is decoded if the output is not regulated by a CV or CL
control loop.
The flip-flops are set by any transition into a decoded state.
This generates a record of whether any of the conditions
(CV, + CL, - CL, UNREG) existed since the last time the flip-
flops were reset. The STATUS RESET input line from the
microcomputer resets the flip-flops.
The status monitor circuit also receives OV SENSE and
THERM inputs. The THERM signal is received from the
power module(s) in the power mesh (see Figure 2-5) and
indicates when an overtemperature condition exists. Note
that when the microcomputer senses the overtemperature
(OT) condition via data bus line D4, it shuts down the
output. This circuit resets automatically and restores the
output approximately 30 seconds after the temperature
drops sufficiently for safe operation.
The OV SENSE input signal indicates when the output’s
overvoltage detector circuit has been tripped and the output
has been shut-down (see overvoltage detector description
below). The THERM and OV SENSE inputs control the OT
and OV outputs of the status monitor. Note that the OT and
OV status are not held in flip-flops. All of status monitor’s
outputs (CVO, CLO, - CLO, OV, OT, and UNREG are
returned to the microcomputer via data bus lines D0-D5
when chip select CS0 is decoded.
2-8
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