Publication 1763-RM001C-EN-P - October 2009
104 Using the High-Speed Counter and Programmable Limit Switch
This bit is transitional and is set by the HSC sub-system. It is up to the
control program to utilize, track if necessary, and clear (0) the overflow
condition.
Overflow conditions do not generate a controller fault.
efesotomasyon.com - Allen Bradley,Rockwell,plc,servo,drive
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