AMD Confidential
User Manual November 21
st
, 2008
Chapter 7: Device Configuration 101
7.15 PCI-X Test Device
This PCI-X Test Device model provides a simulation of a generic PCI-X device. Its main
purpose is to provide BIOS programmers with a tool to test the PCI-X configuration
cycle. This device is implemented as a single-function device.
Interface
The interface varies from system to system. In the AMD Athlon 64 or AMD Opteron
processor-based system configurations, it can be connected to AMD-8131 PCI-X or
AMD-8111 Southbridge devices.
Initialization and Reset State
At creation and reset states, the PCI-X device registers have the default hard-coded
values. By default, the PCI-X device is set to have no I/O, memory-space and interrupt
capability. The PCI-X device has a default Device ID and Vendor ID. At reset, the device
configuration does not change and the values from the device configuration will be
eventually read into the PCI-X registers when the configured system is restarted.
Contents of a BSD
PCI-X register and interrupt signals are saved in the BSD.
Differences from Real Hardware
This is a generic PCI-X device. It doesn't have real a memory buffer and I/O buffer. For
memory and I/O space transaction, if the transaction belongs to this device's memory or
I/O address range, the PCI-X device simply outputs a message to the Log Window which
identifies its memory or I/O cycle.
Interrupt can be de-asserted by doing an I/O transaction. Interrupts can also be de-
asserted manually by using the debugger.
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