AMD Confidential
User Manual November 21
st
, 2008
154 Chapter 10: CPU Debugger
Similar to the t command, single steps the
simulation one instruction, unless the current
instruction is a call, software interrupt, or
repeated string instruction, in which case this
command sets a temporary execution
breakpoint at the instruction sequentially
following the current instruction, and starts
simulation.
Displays, and optionally alters, the contents of
various CPU registers. For a list of register
names that are supported, type R?. Normally,
the display is in the current CPU mode. To
force 16-bit, 32-bit, or 64-bit register display,
type R16, R32, or R64 respectively.
Display 16-bit registers (until the next
instruction).
Display 32-bit registers (until the next
instruction).
Display 64-bit registers (until the next
instruction).
s <Bus> <Device> <Function>
Displays the PCI configuration registers
associated with the given Bus, Device, and
Function number.
Executes [count] instructions. The default value
for [count] is 1.
Disassembles instructions starting, at the given
address and continuing for [length] instructions.
Instructions are disassembled using the current
CPU execution mode.
Displays the version number information for the
attached processor device.
q<a|1> [noncase]
<StartAddress>[,[l|p]]
<[[L]Length] | [EndAddress]>
<Pattern>
Search physical (default) or linear Memory for
pattern and display all or only first
occurrence(s).
Table 10-7: Debugger Commands and Definitions
In general, address and count values can be specified as constants (hex for addresses,
ports, and values; decimal for counts and lengths), or as register names. For addresses,
the CS:, DS:, ES:, FS:, GS:, and SS: prefixes are also allowed.
Address values may be suffixed by „,L‟ to specify a linear address (the default) or „,P‟ to
specify a physical address. Addresses may also be specified by their symbol name.
Precede the symbol name with a # character to distinguish it from a hex constant.
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