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AMD XILINX VEK280 - Page 41

AMD XILINX VEK280
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3/20/24, 12:51 PM
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PMC MIO[42:43] UART0
[Figure 1, callout 9]
This is the primary Versal device PS-side UART interface. MIO42 (RX_IN) and MIO43
(TX_OUT) are connected to FTDI FT4232HL U20 USB-to-Quad-UART bridge port BD
through TI SN74AVC4T245 level-shifters U18 and U271. The FT4232HL U20 port
assignments are listed in the following table.
Table: FT4232HL Port Assignments
FT4232HL U34 Versal Device U1
Port AD JTAG VEK280 JTAG chain
Port BD UART0 PS_UART0 (MIO 42-43)
Port CD UART1 PL_UART1 bank 401
Port DD UART2 U20 system controller UART
The FT4232HL UART interface connections are shown in the following figure.
Figure: FT4232HL UART Connections
For more information on the FT4232HL, see the Future Technology Devices
International Ltd. website.
Note: The FTDI configuration image can be programmed with the Vivado tools.
See the Programming FTDI Devices for Vivado Hardware Manager Support section
in the Vivado Design Suite User Guide: Programming and Debugging (UG908).
Alternatively, a JTAG-SMT2 or similar from Digilent is recommended.

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