HDMI Clock Recovery
The HDMI circuitry includes a Renesas 8T49N241 frequency translator as a jitter
attenuator. VE2802 can output a differential RX recovered clock
(HDMI_RX_REFCLK) for jitter attenuation. The jitter-attenuated clock
(HDMI_8T49N241_OUT) is routed as a reference clock to GTYP Bank 204. The
8T49N241 is used to generate the reference clock for the HDMI transmitter
subsystem. When the HDMI transmitter is used standalone mode (FRL/TMDS) or
pass-through mode (FRL), the 8T49N241 clock synthesizer (U362) operates in free
running mode and uses an external oscillator as the reference. When the HDMI
operation is in pass-through mode (TDMS), the 8T49N241 generates a jitter-
attenuated reference clock to drive the HDMI transmitter subsystem with a phase-
aligned version of the HDMI RX subsystem TMDS clock, so that they are phase
aligned. The 8T49N241 is controlled by the HDMI 2.1 IP via I2C bus, HDMI_I2C_CTL.
HDMI I/O Interface
The HDMI TX and RX I/O signals are assigned to VE2802 XPIO Bank 702. Some of
these signals such as I2C buses, HDMI_TX_SRC, and HDMI_RX_SNK have voltage
translation to 5V connected to the HDMI receptacle. The block diagram in the
following figure shows the I/O signal connections for HDMI TX and RX. A 128-Kbit
EEPROM is provided for storing HDMI EDID metadata in the circuitry.
Figure: HDMI SRC and SNK Control I/O Block Diagram
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