AMD XILINX VEK280 - Page 6

3/20/24, 12:51 PM
Unofficial Document
https://docs.amd.com/internal/api/webapp/print/d54fa025-f5b0-4797-be6e-41b3e31f9548
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XCVE2802, VSVH2802 package
Form factor: see Board Specifications
Onboard configuration from:
USB-to-JTAG bridge
JTAG pod 2 mm 2x7 flat cable connector
microSD card (PS MIO I/F)
Quad SPI (QSPI)/eMMC (system controller I/F)
OSPI
Clocks
Versal device bank 702/5/6 RC21008A SYS_CLK_0/1/2 (DIMM) 200 MHz
Versal device bank GTY205/6 RC21008A_GTCLK1_OUT6/7 100 MHz
Versal device bank GTY106 RC21008A RC21008A_GTCLK1_OUT8 156.25
MHz
Versal device bank GTY106 626L15625 HSDP_156_25_REFCLK 156.25
MHz
Versal device bank GTY204 8T49N241 HDMI_8T49N241_OUT design
dependent
Versal device bank GTY204 TMDS1204 HDMI_RCLK_OUT design
dependent
Versal device bank 503 RC21008A PS_REF_CLK 33.3333 MHz
Versal device bank 503 RTC Xtal 32.768 kHz
Three pin-efficient mode LPDDR4 interfaces (2x32-bit 4 GB components each)
XPIO triplet 1 (banks 700, 701, 702)
XPIO triplet 2 (banks 703, 704, 705)
XPIO triplet 3 (banks 706, 707, 708)
PL FMCP HSPC (FMC+) connectivity
FMCP1 HSPC full LA[00:33] bus
PL GPIO connections
PL UART1 to FTDI
PL GPIO DIP switch (4-position)
PL GPIO LEDs (four)
PL GPIO pushbuttons (two)
PL SYSCTLR_GPIO[0:7]
PL 1588_GPIO[0:7, SMA_CLK I/O]
32 PL GTYP transceivers (8 quads)