ASROCK CML-HDV/M.2 TPM R2.0 - Page 47

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CML-HDV/M.2 TPM R2.0
DRAM Reference Clock
Select Auto for optimized settings.
DRAM Frequency
If [Auto] is selected, the motherboard will detect the memory module(s) inserted
and assign the appropriate frequency automatically.
Primary Timing
CAS# Latency (tCL)
e time between sending a column address to the memory and the beginning of the data
in response.
RAS# to CAS# Delay and Row Precharge (tRCDtRP)
RAS# to CAS# Delay : e number of clock cycles required between the opening of a row
of memory and accessing columns within it.
Row Precharge: e number of clock cycles required between the issuing of the precharge
command and opening the next row.
RAS# Active Time (tRAS)
e number of clock cycles required between a bank active command and issuing the
precharge command.
Command Rate (CR)
e delay between when a memory chip is selected and when the rst active command can
be issued.
Secondary Timing
Write Recovery Time (tWR)
e amount of delay that must elapse aer the completion of a valid write
operation, before an active bank can be precharged.
Refresh Cycle Time (tRFC)
e number of clocks from a Refresh command until the rst Activate command to
the same rank.
RAS to RAS Delay (tRRD_L)
e number of clocks between two rows activated in dierent banks of the same
rank.