ASROCK H610M-ITX/eDP - Page 57

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H610M-IT X/eDP
DRAM Timing Conguration
DRAM Reference Clock
Select Auto for optimized settings.
DRAM Frequency
If [Auto] is selected, the motherboard will detect the memory module(s) inserted
and assign the appropriate frequency automatically.
DRAM Gear Mode
High gear is good for high frequency.
Primary Timing
CAS# Latency (tCL)
e time between sending a column address to the memory and the beginning of the data
in response.
RAS# to CAS# Delay (tRCD)
e number of clock cycles required between the opening of a row of memory and
accessing columns within it.
Row Precharge (tRP)
e number of clock cycles required between the issuing of the precharge command and
opening the next row.
RAS# Active Time (tRAS)
e number of clock cycles required between a bank active command and issuing the
precharge command.
Command Rate (CR)
e delay between when a memory chip is selected and when the rst active command can
be issued.
Secondary Timing
Write Recovery Time (tWR)
e amount of delay that must elapse aer the completion of a valid write operation,
before an active bank can be precharged.
Refresh Cycle Time (tRFC)