ASROCK X299E-ITX/ac - Page 58

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CPU BCLK Amplitude
Congure the BCLK Amplitude for ClockGen.
SRC BCLK Amplitude
Congure the BCLK Amplitude for SRC.
SATA BCLK Amplitude
Congure the BCLK Amplitude for SATA.
CPU1 Slew Rate
Congure the CPU Slew Rate. Adjust the BCLK signal by dening the maximum
change rate of the output voltage. Higher value will result in a shorter signal rising
time.
CPU2/SRC1 Slew Rate
Congure the CPU2/SRC1 Slew Rate. Adjust the BCLK signal by dening the
maximum change rate of the output voltage. Higher value will result in a shorter
signal rising time.
SRCO Slew Rate
Congure the SRCO Slew Rate. Adjust the BCLK signal by dening the maximum
change rate of the output voltage. Higher value will result in a shorter signal rising
time.
SATA Slew Rate
Congure the SRCO Slew Rate. Adjust the BCLK signal by dening the maximum
change rate of the output voltage. Higher value will result in a shorter signal rising
time.
CPU PLL ORT
Congure the CPU PLL ORT. Overshoot Reduction Technology improves the
BCLK signal to decrease overshoot/undershoot.
PCIE PLL ORT
Congure the PCIE PLL ORT. Overshoot Reduction Technology improves the
BCLK signal to decrease overshoot/undershoot.
CPU Output Divider
Congure the CPU output divider.
SRC Output Divider
Congure the SRC output divider.