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CPU BCLK Amplitude
Congure the BCLK Amplitude for ClockGen.
SRC BCLK Amplitude
Congure the BCLK Amplitude for SRC.
SATA BCLK Amplitude
Congure the BCLK Amplitude for SATA.
CPU1 Slew Rate
Congure the CPU Slew Rate. Adjust the BCLK signal by dening the maximum
change rate of the output voltage. Higher value will result in a shorter signal rising
time.
CPU2/SRC1 Slew Rate
Congure the CPU2/SRC1 Slew Rate. Adjust the BCLK signal by dening the
maximum change rate of the output voltage. Higher value will result in a shorter
signal rising time.
SRCO Slew Rate
Congure the SRCO Slew Rate. Adjust the BCLK signal by dening the maximum
change rate of the output voltage. Higher value will result in a shorter signal rising
time.
SATA Slew Rate
Congure the SRCO Slew Rate. Adjust the BCLK signal by dening the maximum
change rate of the output voltage. Higher value will result in a shorter signal rising
time.
CPU PLL ORT
Congure the CPU PLL ORT. Overshoot Reduction Technology improves the
BCLK signal to decrease overshoot/undershoot.
PCIE PLL ORT
Congure the PCIE PLL ORT. Overshoot Reduction Technology improves the
BCLK signal to decrease overshoot/undershoot.
CPU Output Divider
Congure the CPU output divider.
SRC Output Divider
Congure the SRC output divider.