A785G3/A780L3/A780L3G BIOS Manual
32
DRAM Timing Configuration
BIOS SETUP UTILITY
vxx.xx (C)Copyright 1985-200x, American Megatrends, Inc.
Select Screen
Select Item
Change Option
General Help
Save and Exit
Exit
+-
F1
F10
ESC
DRAM Timing Config uration
Memory CLK :
CAS Latency(Tcl) :
RAS/CAS Delay(Trcd) :
Row Precharge Time(Trp):
Min Active RAS(Tras) :
RAS/RAS Delay(Trrd) :
Row Cycle (Trc) :
Command Rate(CR) :
Write Recover Time(Twr):
> Memory Configuration
> ECC Configuration
> BIOSTAR Memory Insight
Memory Clock Mode [Auto]
Memclock Value [DDR3-800]
DRAM Timing Mode [Auto]
Performance
Memory Configuration
BIOS SETUP UTILITY
vxx.xx (C)Copyright 1985-200x, American Megatrends, Inc.
Select Screen
Select Item
Change Option
General Help
Save and Exit
Exit
+-
F1
F10
ESC
Memory Configuration
Bank Interleaving [Auto]
Channel Interleaving [XOR of Address bit]
Enable Clock to All DIMMs [Disabled]
MemClk Tristate C3/ATLVID [Disabled]
Memory Hole Remapping [Enabled]
DCT Unganged Mode [Always]
Power Down Enable [Disabled]
Page Smashing [Disabled]
Enable Bank Memory
Interleaving
Performance
Bank Interleaving
Bank Interleaving is an advanced chipset technique used to improve memory
performance. Memory interleaving increases bandwidth by allowing simultaneous
access to more than one piece of memory.
Options: Auto (Default)