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Cisco ASR 9000 Series Aggregation Services Router Overview and Reference Guide
OL-17501-09
Chapter 2      Functional Description
Ethernet Line Cards
the path from the two bridge FPGAs to the fabric interface chip is 60-Gbps. The total bandwidth from 
fabric interface chip to the backplane is 46-Gbps redundant. The fabric interface chip connects through 
four 23-Gbps links to the backplane.
Each NPU can handle up to 15-Gbps of line rate traffic (depending on the packet size and processing 
requirements).   The line cards can handle many different Ethernet protocols to provide Layer2/Layer3 
switching. Each NPU can handle 30-Gbps of line rate data in a fully subscribed configuration. All 
switching between ports is handled on the RSP/RP card, which is connected through the backplane to 
all line cards. VOQ is implemented in the fabric interface chip both on the line cards and on the RSP/RP 
card, which assures that all ingress data paths have equal access to their egress data ports. 
Although the usable fabric bandwidth over the backplane from the fabric interface ASIC is 80-Gbps, 
only up to 40-Gbps (usable data) flows over the interface plus any added overhead traffic (46-Gbps). 
40-Port Gigabit Ethernet (40x1GE) Line Card
The 40-port Gigabit Ethernet (40x1GE) line card has 40 ports connected to SFP modules handling 40 
Gigabit Ethernet interfaces through SGMII connections to four NPUs. The 40 SFP ports are organized 
into four blocks of 10 ports. Each block of 10 ports connects to one NPU through an SGMII serial bus 
interface.
The 40x1GE line card is available in base, extended, and low-queue versions. All versions are 
functionally equivalent, with the extended version of the line card providing typically twice the service 
scale of the base line card.
Figure 2-17 shows a block diagram for the 40x1GE line card, and Figure 2-18 shows the front panel 
connectors and indicators.
Figure 2-17 40-Port Gigabit Ethernet (40x1GE) Line Card Block Diagram
40x1GE
Line Card
243067
B
a
c
k
p
l
a
n
e
Fabric
Interface
Chip
GE
PHY
FPGA
NPU
NPU
FPGA
10 x SFP
10 x SFP
NPU
NPU
10 x SFP
10 x SFP
CPU