DRZ9255
HX-D2
- 10 -
051-6708-90 AK4121VF Asynchronous Sample Rate Converter
Terminal Description
pin 1: FILT : O : PLL filter output.
pin 2: A VSS : - : Negative voltage supply for analog section.
pin 3: PDN :IN: Power down & reset signal input.
pin 4: S MUTE :IN: The soft muting command input.
pin 5: DEM 0 :IN: De-emphasis Frequency Selection.
pin 6: DEM 1 :IN: De-emphasis Frequency Selection.
pin 7: I LR CK : IN: Left/Right clock input for the input signal.
pin 8: I BI CK :IN: Bit clock input for the input signal.
pin 9: SDT I :IN: The serial data input.
pin 10: I DIF 0 :IN: Input data format select.
pin 11: I DIF 1 :IN: Input data format select.
pin 12: I DIF 2 :IN: Input data format select.
pin 13: C MODE 0 :IN: The clock mode select.
pin 14: C MODE 1 :IN: The clock mode select.
pin 15: C MODE 2 :IN: The clock mode select.
pin 16: O DIF 0 :IN: Output data format select.
pin 17: O DIF 1 :IN: Output data format select.
pin 18: SDT O : O : The audio serial data output.
pin 19: O BI CK :I/O: Bit clock input/output for the output signal.
pin 20: O LR CK :I/O: Left/Right clock input/output for the output
signal.
pin 21: MASTER CLK :IN: Master clock input.
pin 22: T VDD : - : Positive voltage supply for output-buffer.
pin 23: D VSS : - : Digital ground.
pin 24: VDD : - : Positive voltage supply.
Table 1. Master/Slave control
Cmode 2 Cmode 1 Cmode 0 Master CLK Master/Slave
(pin 15) (pin 14) (pin 13) (pin 21) (Output port)
L L L 256fso(fso to 96kHz) Master
L L H 384fso(fso to 96kHz) Master
L H L 512fso(fso to 48kHz) Master
L H H 768fso(fso to 48kHz) Master
H L L Connect to DVSS Slave
H H H Connect to DVSS Master(bypass mode)
Table 2. Input Audio data Formats
I DIF 2 I DIF 1 I DIF 0 SDT I format I BI CK (slave)
(pin 12) (pin 11) (pin 10) (pin 9) (pin 8)
L L L 16bit LSB Justified 32 or less
L L H 20bit LSB Justified 40 or less
L H L 20bit MSB Justified 40 or less
L H H 20/16bit I2C compat. 32/40fs or less
H L L 24bit LSB Justified 48 or less
Table 3. Output Audio data Formats
O DIF 1 O DIF 0 SDT O format O BI CK O BI CK
(pin 17) (pin 16) (pin 18) (Slave) (Master)
L L 16bit LSB Justified 64fs 64fs
L H 20bit LSB Justified 64fs 64fs
H L 20/16bit MSB Justif. 32/40fs or less 64fs
H H 20/16bit I2C compat. 32/40fs or less 64fs
Table 4. De-emphasis filter control
DEM 1 (pin 6) DEM 0 (pin 5) De-emphasis filter
L L 44.1kHz
L H off
H L 48.0kHz
L H 32.0kHz
051-6071-08 BA5825FP-E2 Quad Motor Drivers
Truth Table
MUTE CNT CH1,2,3 CH4
(pin 9) (pin 21) output output
H H MUTE OFF LD ON
H L MUTE OFF SL ON
L H MUTE ON LD ON
L L MUTE ON MUTE ON
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Level
Shift
Level
Shift
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Level
Shift
Level
Shift
2-ch OP in-
2-ch OP out
1-ch OP in-
1-ch OP out
REG-Base
REG-FB
Pr-Ground
Mute in
Power GND
Power Vcc
1-ch drive out-
1-ch drive out+
2-ch drive out-
2-ch drive out+
Pre VCC
Bias
3-ch OP in-
3-ch OP out
SL OP in-
SL OP out
Loading in-
Control in
Power Ground
Power Vcc
4-ch drive out-
4-ch drive out+
3-ch drive out-
3-ch drive out+
2.4V
2.4V
L IN
L A GND
L OUT
A V-
A V+
R OUT
R A GND
R IN
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
ZCEN
CS_
S Data I
D VDD
D GND
S CLK
S Data O
Mute In
Logic
Control
051-5036-90 PGA2310UA Stereo Volume Controller
Terminal Description
pin 1: ZCEN :IN: Zero Cross Enable signal input.
pin 2: CS IN : IN: The chip select command input.
pin 3: S DATA IN :IN: The serial data input.
pin 4: D VDD : - : Positive voltage supply for digital section.
pin 5: D GND : - : Digital ground.
pin 6: S CLK :IN: The serial clock input.
pin 7: S DATA OUT : O : The serial data output.
pin 8: MUTE IN :IN: Mute command input.
pin 9: R A IN :IN: Right channel audio signal input.
pin 10: R A GND : - : Right channel audio signal ground.
pin 11: R A OUT : O : Right channel audio signal output.
pin 12: A V+ : - : Positive voltage supply for analog section.
pin 13: A V- : - : Negative voltage supply for analog section.
pin 14: L A OUT : O : Left channel audio signal output.
pin 15: L A GND : - : Left channel audio signal ground.
pin 16: L A IN :IN: Left channel audio signal input.