DRZ9255
HX-D2
- 9 -
051-6373-18 AK4112BVF Digital Interface Receiver
Terminal Description
pin 1: D VDD : - : Positive voltage supply for the digital sec-
tion.
pin 2: D VSS : - : Digital ground.
pin 3: T VDD : - : Positive voltage supply for output-buffer.
pin 4: VALIDITY : O : Validity flag output in the parallel mode.
: TX : O : Transmit channel (through data) output in
serial mode.
pin 5: XT I :IN: Oscillation terminal.
pin 6: XT O : O : Oscillation terminal.
pin 7: PDN :IN: Power down & reset signal input.
pin 8: RESIST : - : The resistor connection.
pin 9: A VDD : - : Positive voltage supply for analog section.
pin 10: A VSS : - : Negative voltage supply for analog section.
pin 11: RX 1 :IN: The receiver channel 1 in serial mode.
pin 12: DIF 0 :IN: The audio data format selection in parallel
mode, refer Table 1.
: RX 2 :IN: The receiver channel 2 in serial mode.
pin 13: DIF 1 :IN: The audio data format selection in parallel
mode, refer Table 1.
: RX 3 :IN: The receiver channel 3 in serial mode.
pin 14: DIF 2 :IN: The audio data format selection in parallel
mode, refer Table 1.
: RX 4 :IN: The receiver channel 4 in serial mode.
pin 15: PCM DET : O : Non-PCM detect. L = Non detect.
pin 16: PARA/SERI :IN: Parallel("H")/Serial("L") mode select input.
pin 17: FS96 : O : 96kHz Sampling detect.
RX mode
H : fs = 88.2kHz or more
L : fs = 54kHz or less
Xtal mode
H : XFS96 = 1
L : XFS96 = 0
pin 18: ERF : O : Unlock & Parity error output. L = No error.
pin 19: LR CK I/O :I/O: Left/Right clock.
pin 20: SDT O : O : The audio serial data output.
pin 21: BI CK :I/O: Audio serial data clock.
pin 22: D AUX :IN: Auxiliary audio serial data input.
pin 23: MCK O 2 : O : Master clock output, refer Table 2.
pin 24: MCK O 1 : O : Master clock output, refer Table 2.
pin 25: OCK Sel 0 :IN: Output clock select in parallel mode.
refer Table 2.
: CSN :IN: Chip select input in serial mode.
pin 26: OCK Sel 1 :IN: Output clock select in parallel mode.
refer Table 2.
: C CLK :IN: Control clock input in serial mode.
pin 27: CM 1 : IN: Master clock operation select input in par-
allel mode, refer Table 3.
: CDTI : IN: Control data input in serial mode.
pin 28: CM 0 : IN: Master clock operation select input in par-
allel mode, refer Table 3.
: CDTO : O : Control data output in serial mode.
Table 1. Audio data format
DIF 2 DIF 1 DIF 0 D AUX SDT O LR CK BI CK
(pin 14) (pin 13) (pin 12) (pin 22) (pin 20) (pin 19) (pin 21)
24bit 16bit H/L 64fs
0 0 0 Left Right
justified justified Output Output
24bit 18bit H/L 64fs
0 0 1 Left Right
justified justified Output Output
24bit 20bit H/L 64fs
0 1 0 Left Right
justified justified Output Output
24bit 24bit H/L 64fs
0 1 1 Left Right
justified justified Output Output
24bit 24bit H/L 64fs
1 0 0 Left Left
justified justified Output Output
24bit 24bit L/H 64fs
101
I2S I2S Output Output
24bit 24bit H/L 64-128fs
1 1 0 Left Left
justified justified Intput Input
24bit 24bit H/L 64-128fs
111
I2S I2S Intput Input
Table 2. Master clock frequency select
OCK S 1 OCK S 0 MCK O 1 MCK O 2
(pin 26) (pin 25) (pin 24) (pin 23) X'tal fs(kHz)
32.0
0 0 256fs 256fs 256fs 44.1
48.0
96.0
32.0
0 1 256fs 128fs 256fs 44.1
48.0
96.0
32.0
1 0 512fs 256fs 512fs 44.1
48.0
1 1 - - Test Mode - -
Table 3. Clock operation mode select
CM 1 CM 0 Clock FS96 SDT O
(pin 27) (pin 28) UNLOCK PLL X'tal source (pin 17) (pin 20)
0 0 x ON OFF PLL RFS96 RX
0 1 x OFF ON X'tal XFS96 D AUX
1 0 0 ON ON PLL RFS96 RX
1 0 1 ON ON X'tal XFS96 D AUX
1 1 x ON ON X'tal XFS96 D AUX
To Next Page
Loading...
