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Clevo P955ER - Page 56

Clevo P955ER
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Schematic Diagrams
B - 6 Processor 4/7
B.Schematic Diagrams
Processor 4/7
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
NEAR CPU
CAD Note: Capacitor need to be placed
close to buffer output pin
VCCST_PWRGD
FLOAT FOR SKL
GND FOR CNL
CFG 1.0V 0V DESCRIPTION
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
NORM
HALF-SWING FULL-SWING
DISABLED
ENABLED
ENABLED
NORM
NORM
DISABLED
DISABLED
PCHLESS
ENABLED DISABLED
RESET# BIOS REQ
DISABLED ENABLED
PRESENT NOT PRESENT
ACTIVATE NOT ACTIVATED
PMSYNC2.0 LEGACY
ASYNCHRONOUS
RESERVED
RESERVED
STALL
REVERSE
ENABLED
SYNCHRONOUS
EAR
PHYSICAL_DEBUG_ENABLED
PEG0CFGSEL[0]
DP_PRESENCE
PEG0CFGSEL[1]
PEG_DEFER_TRAINING
CFG UNLOCK
SAFE MODE BOOT
SVID NOT PRESENT
DMI_AC_COUPLED DC COUPLED AC COUPLED
SYNC AND AYNC MODE
STALL
PEG_LANE_REVERSAL -SEE PCIE CHAPTER
PCHLESS MODE
INTERNAL USE ONLY
* ALL CFG 0 = PHYSICAL STRAP LOW ON BOARD
* ALL CFG 1 = NO TERMAINATION ON BOARD DEFAULT HIGH
CFG6 CFG5 PEG CONFIG
0V
RESERVED
X 8 X 4 X 4
0V
10V
10V
0V
10V
10V
0V X 8 X 8
X 16
PEG CONFIG TABLE
* ALL CFG 0 = PHYSICAL STRAP HIGH
* ALL CFG 1 = PHYSICAL STRAP LOW
CFG[6:5] 11:DEFAULT X16
10:2X8; 01:RESERVED
00:X8,X4,X4
H_PROCHOT#_RH_PROCHOT#
CFG_RCOMP
CPU_VIDALERT_N
SKL_XDP_MBP_0
SKL_XDP_MBP_1
SKL_MBP_2
SKL_MBP_3
H_TDO
H_TCK
H_TRST#
H_PREQ#
H_PRDY#
CFG4
CFG0
VCCST_PWRGD_CPU
H_TDO
H_TCK
H_SKTOCC_N
VCCST_PWRGD
VCCST_PWRGD
H_PROCHOT#
H_PECI_R
H_PM_DOWN_R
H_SKTOCC_N
H_CATERR_N
H_TDI
H_TMS
1.05V_VCCST
1.05DX_VCCSTG
1.05DX_VCCSTG
1.05V_VCCST
VDD3
3.3VA
1.05V_VCCST
1.05V_VCCST
H_PROCHOT#58,64
PCH_CPU_BCLK_R_DN35
PCH_CPU_BCLK_R_DP35
PCH_CPU_PCIBCLK_R_DN35
PCH_CPU_PCIBCLK_R_DP35
CPU_24MHZ_R_DN35
CPU_24MHZ_R_DP35
H_CPU_SVIDCLK58
H_CPU_SVIDDAT58
H_CPU_SVIDALRT#58
H_PROCHOT_EC39
ALL_SYS_PWRGD11,38,39,58
DDR_VTT_PG_CTRL57
VDD327,30,31,33,36,38,39,42,47,48,49,51,52,53,54,55,56,57,63,64
1.05V_VCCST7,54,56,58
3.3VA30,33,34,36,38,53,54
PLTRST_CPU_N32
H_PM_SYNC32
H_PWRGD33
H_PM_DOWN32
PCH_THERMTRIP#32
H_SKTOCC_N30,34
H_PECI39
1.05DX_VCCSTG7,33,54
Title
Size Document Number R e v
Date: Sheet
of
6-71-P95E0-D02A
D02A
[05]Processor E/13-CLK/JTAG
A3
572Monday, February 12, 2018
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
P950ER
Title
Size Document Number R e v
Date: Sheet
of
6-71-P95E0-D02A
D02A
[05]Processor E/13-CLK/JTAG
A3
572Monday, February 12, 2018
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
P950ER
Title
Size Document Number R e v
Date: Sheet
of
6-71-P95E0-D02A
D02A
[05]Processor E/13-CLK/JTAG
A3
572Monday, February 12, 2018
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
P950ER
R595 100_04
CPU
R227 10K_04CPU
R222
56.2_1%_04
CPU
R223
220_04
CPU
R500 1K_04CPU
R195 499_1%_04
CPU
R592 51_04
CPU
S
D
G
Q12A
MTDK3S6R
CPU
2
61
R201
100K_04
CPU
R590
49.9_1%_04
CPU
R593 *1K_04CPU
S
D
G
Q12B
MTDK3S6R
CPU
5
34
R225 *1K_04CPU
C438
*0.01u_50V_X7R_04
CPU
R203
1K_04
CPU
R230 20_1%_04CPU
Q9
2SK3018S3
CPU
G
DS
R214
100K_04
CPU
R594 1K_04CPU
5 OF 13
??
?
?U172E
CFL_H_62_INT_IP_CRB_CFLH
VIDSOUT
BH29
DDR_VTT_CNTL
BT13
VCCST_PWRGD
H13
PM_SYNC
BM34
PM_DOWN
BP31
PECI
BT34
CFG_18
BN22
PROC_TCK
BR28
CFG_19
BP22
THERMTRIP#
J31
PROC_TDO
BT28
CFG_0
BN25
PROC_TRST#
BP30
CFG_1
BN27
PROC_SELECT#
BN1
ZVM#
AT13
SKTOCC#
BR33
CFG_2
BN26
CFG_RCOMP
BT25
CFG_3
BN28
PROC_PREQ#
BL30
CFG_4
BR20
CFG_10
BT23
RESET#
BP35
CFG_5
BM20
CLK24N
D31
PROCPWRGD
BT31
CFG_11
BT22
CFG_6
BT20
BPM#_0
BR27
VIDSCK
BH32
BCLKN
A32
PCI_BCLKN
C36
BPM#_1
BT27
CFG_7
BP20
CFG_12
BM19
CLK24P
E31
CFG_8
BR23
CFG_13
BR19
BPM#_2
BM31
BCLKP
B31
PCI_BCLKP
D35
BPM#_3
BT30
PROCHOT#
BR30
CFG_9
BR22
CFG_14
BP19
RSVD2
AY13
CFG_15
BT19
RSVD1
AU13
PROC_PRDY#
BP27
CFG_16
BP23
CATERR#
BM30
PROC_TDI
BL32
MSM#
AW13
PROC_TMS
BP28
CFG_17
BN23
VIDALERT#
BH31
R186 1K_04
CPU
R588
*0_04
CPU
R206 60.4_1%_04
CPU
C403
47p_50V_NPO_04
CPU
R231 *0402_shortCPU
R221
100_04
CPU
R226 *1K_04CPU
R591 *1K_04CPU
R228 100K_04
CPU
C455
*0.1u_16V_X7R_04
CPU
R229 *1K_04CPU
Sheet 5 of 72
Processor 4/7

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