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Clevo W251ESQ - Processor Interface Schematics

Clevo W251ESQ
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Schematic Diagrams
Processor 1/7-DMI, FDI, PEG B - 3
B.Schematic Diagrams
Processor 1/7-DMI, FDI, PEG
Sheet 2 of 50
Processor 1/7-DMI,
FDI, PEG
R140 24.9_1%_04
PTH1
10K_1%_NTC_06
12
R654
10K_1%_04
C181 0.22u_10V_X5R_04
C176 0.22u_10V_X5R_04
C159 0.22u_10V_X5R_04
C179 0.22u_10V_X5R_04
C147 0.22u_10V_X5R_04
C157 0.22u_10V_X5R_04
C178 0.22u_10V_X5R_04
C180 0.22u_10V_X5R_04
C190 0.22u_10V_X5R_04
C175 0.22u_10V_X5R_04
C165 0.22u_10V_X5R_04
C174 0.22u_10V_X5R_04
C166 0.22u_10V_X5R_04
C167 0.22u_10V_X5R_04
C168 0.22u_10V_X5R_04
C156 0.22u_10V_X5R_04
3.3 V
W/O CPU THERMAL IÉ,
PCB·Å«×¶q´ú¥Î
6-17-10300-730
R508
24.9 _1%_04
for ¦@¥Îr3.4_831
R509
1K_1%_04
Ivy Bridge Quad Core 55W
Q28
*TMP20
NC
1
GND
2
VO
3
GND
5
VCC
4
Ivy Bridge Dual Core 35W
PCI EXPRESS* - GRAPHICS
DMI
Intel(R) FDI
eDP
U36A
Iv y Bridge_rPGA_2DPC_Rev 0p61
DMI_RX#[0]
B27
DMI_RX#[1]
B25
DMI_RX#[2]
A25
DMI_RX#[3]
B24
DMI_RX[0]
B28
DMI_RX[1]
B26
DMI_RX[2]
A24
DMI_RX[3]
B23
DMI_TX#[0]
G21
DMI_TX#[1]
E22
DMI_TX#[2]
F21
DMI_TX#[3]
D21
DMI_TX[0]
G22
DMI_TX[1]
D22
DMI_TX[3]
C21
DMI_TX[2]
F20
FDI 0_TX#[0]
A21
FDI 0_TX#[1]
H19
FDI 0_TX#[2]
E19
FDI 0_TX#[3]
F18
FDI 1_TX#[0]
B21
FDI 1_TX#[1]
C20
FDI 1_TX#[2]
D18
FDI 1_TX#[3]
E17
FDI 0_TX[0]
A22
FDI 0_TX[1]
G19
FDI 0_TX[2]
E20
FDI 0_TX[3]
G18
FDI 1_TX[0]
B20
FDI 1_TX[1]
C19
FDI 1_TX[2]
D19
FDI 1_TX[3]
F17
FDI 0_FSYNC
J18
FDI 1_FSYNC
J17
FDI _INT
H20
FDI 0_LSYNC
J19
FDI 1_LSYNC
H17
PEG _ICO MPI
J22
PEG_ICOMPO
J21
PEG_RCOMPO
H22
PEG_RX#[0]
K33
PEG_RX#[1]
M35
PEG_RX#[2]
L34
PEG_RX#[3]
J35
PEG_RX#[4]
J32
PEG_RX#[5]
H34
PEG_RX#[6]
H31
PEG_RX#[7]
G33
PEG_RX#[8]
G30
PEG_RX#[9]
F35
PEG _RX#[ 10]
E34
PEG _RX#[ 11]
E32
PEG _RX#[ 12]
D33
PEG _RX#[ 13]
D31
PEG _RX#[ 14]
B33
PEG _RX#[ 15]
C32
PEG_RX[0]
J33
PEG_RX[1]
L35
PEG_RX[2]
K34
PEG_RX[3]
H35
PEG_RX[4]
H32
PEG_RX[5]
G34
PEG_RX[6]
G31
PEG_RX[7]
F33
PEG_RX[8]
F30
PEG_RX[9]
E35
PEG_RX[10]
E33
PEG_RX[11]
F32
PEG_RX[12]
D34
PEG_RX[13]
E31
PEG_RX[14]
C33
PEG_RX[15]
B32
PEG_TX#[0]
M29
PEG_TX#[1]
M32
PEG_TX#[2]
M31
PEG_TX#[3]
L32
PEG_TX#[4]
L29
PEG_TX#[5]
K31
PEG_TX#[6]
K28
PEG_TX#[7]
J30
PEG_TX#[8]
J28
PEG_TX#[9]
H29
PEG_TX#[10]
G27
PEG_TX#[11]
E29
PEG_TX#[12]
F27
PEG_TX#[13]
D28
PEG_TX#[14]
F26
PEG_TX#[15]
E25
PEG_TX[0]
M28
PEG_TX[1]
M33
PEG_TX[2]
M30
PEG_TX[3]
L31
PEG_TX[4]
L28
PEG_TX[5]
K30
PEG_TX[6]
K27
PEG_TX[7]
J29
PEG_TX[8]
J27
PEG_TX[9]
H28
PEG_TX[10]
G28
PEG_TX[11]
E28
PEG_TX[12]
F28
PEG_TX[13]
D27
PEG_TX[14]
E26
PEG_TX[15]
D25
eDP_AUX
C15
eDP_AUX#
D15
eDP_TX[0]
C17
eDP_TX[1]
F16
eDP_TX[2]
C16
eDP_TX[3]
G15
eDP_TX#[0]
C18
eDP_TX#[1]
E16
eDP_TX#[2]
D16
eDP_TX#[3]
F15
eDP_C OMPIO
A18
eDP_H PD
B16
eDP_I COMPO
A17
C682
*0.1 u_10V_X7R _04
C686
*0.1u_10V_X7R_04
SC70-5 & SC70-3
Co-lay
Q29
*G711ST9U
OUT
1
VCC
2
GND
3
3.3 V
1.05VS_VTT
1.0 5VS_VTT
1.05VS_VTT
DMI_TXP320
DMI_TXP220
DMI_TXP120
DMI_TXP020
DMI_TXN220
DMI_TXN120
DMI_TXN020
DMI_RXN120
DMI_RXN020
DMI_TXN320
DMI_RXP020
DMI_RXN320
DMI_RXN220
DMI_RXP320
DMI_RXP220
DMI_RXP120
FDI_LSYNC020
FDI_INT20
FDI_FSYNC120
FDI_FSYNC020
FDI _TXN 120
FDI _TXN 020
FDI_LSYNC120
FDI _TXN 420
FDI _TXN 320
FDI _TXN 220
FDI _TXN 720
FDI _TXN 620
FDI _TXN 520
FDI _TXP220
FDI _TXP120
FDI _TXP020
FDI _TXP620
FDI _TXP520
FDI _TXP420
FDI _TXP320
THERM_VOLT 34
FDI _TXP720
PEG_RX#1 12
PEG_RX#4 12
PEG_RX#2 12
PEG_RX#0 12
PEG_RX#3 12
PEG_RX#7 12
PEG_RX7 12
PEG_RX#5 12
PEG_RX#6 12
PEG_RX2 12
PEG_RX4 12
PEG_RX5 12
PEG_RX6 12
PEG_RX0 12
PEG_RX3 12
PEG_TX#5 12
PEG_TX#2 12
PEG_TX#3 12
PEG_RX1 12
PEG_TX#1 12
PEG_TX#0 12
PEG_TX#7 12
PEG_TX6 12
PEG_TX#4 12
PEG_TX#6 12
PEG_TX4 12
PEG_TX0 12
PEG_TX3 12
PEG_TX5 12
PEG_TX1 12
PEG_TX7 12
PEG_TX2 12
ED P_HPD
ED P_CO MPI O
Ivy Bridge LV/ULV 25/17W
H17
H8_0D4_4
H14
H8_0D4_4
H9
H8 _0D4_4
Ivy Bridge Processor 1/7 ( DMI,PEG,FDI )
CPU
CAD NOTE: PEG_ICOMPI and RCOMPO signals
should be shorted and routed with
- max length = 500 mils
- typical impedance = 43 mohms
PEG_ICOMPO signals should be routed with
- max length = 500 mils
- typical impedance = 14.5 mohms
CAD NOTE: DP_COMPIO and ICOMPO signals
should be shorted near balls and routed with
- typical impedance < 25 mohms
EDP HPD Function Disable
EDP_HPD: Pull-up10K- DISABLED HPD
PEG_TX#_7
PEG_TX#_3
PEG_TX#_0
PEG_TX#_1
PEG_TX#_4
PEG_TX#_6
PEG_TX#_2
PEG_TX#_5
DP Compensation Signal
PEG_IRCOMP_R
1:2 (4mils:8mils)
PLACE NEAR U3
20 mil
3
2
1
PEG_TX_6
PEG_TX_4
PEG_TX_2
PEG_TX_1
PEG_TX_5
PEG_TX_3
PEG_TX_7
PEG_TX_0
2012 Ivy DDR3-1600 and DDR3L-1333 Support.
2012 Ivy Bridge Same TDP as Sandy Bridge.
PEG Compensation Signal
2012 Ivy Bridge Socket compatible with Sandy Bridge.
2012 Ivy DX11 Support, 3 Simultaneous Displays.
2012 Ivy PCIe*Gen3.0(PEGX16).

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