Z0301
R105 56_04
C437 *0.1u_10V_X5R_04
R107 *100K_04
R302
4.99K_1%_04
R338 *43_1%_04
R343 *10mil_04
S
D
G
Q21A
*MTDK5S6R
2
61
R100 *1K_04
R303 *0_04
R101 130_1%_04
CLOCKS
MISCTHERMALPWR MANAGEMENT
DDR3
MISC
JTAG & BPM
U21B
FOXCONN PZ98821-362B-01H
SM_RCOMP[1]
A5
SM_RCOMP[2]
A4
SM_DRAMRST#
R8
SM_RCOMP[0]
AK1
BCLK#
A27
BCLK
A28
DPLL_REF _CLK#
A15
DPLL_REF_CLK
A16
CATERR#
AL33
PECI
AN33
PROCHOT#
AL32
TH ER MTR IP#
AN32
SM_DRAMPWROK
V8
RESET#
AR33
PRDY #
AP29
PREQ#
AP27
TC K
AR26
TMS
AR27
TRS T#
AP30
TDI
AR28
TDO
AP26
DBR#
AL35
BPM#[0]
AT28
BPM#[1]
AR29
BPM#[2]
AR30
BPM#[3]
AT30
BPM#[4]
AP32
BPM#[5]
AR31
BPM#[6]
AT31
BPM#[7]
AR32
PM_SYNC
AM34
SKTOCC#
AN34
PROC_SELECT#
C26
UNCOREPWRGOOD
AP33
R342 *10mil_04
R331 *51_04
R341 *10mil_04
R336 *10mil_04
R305
1K_04
R339 10K_04
R106 62_04
R102
200_1%_04
R327 140_1%_04
C167
47p_50V_NPO_04
C371
0.047u_10V_X7R_04
R334 51_04
R337 *75_1%_04
S
D
G
Q21B
*MTDK5S6R
5
34
R314 200_1%_04
R304 1K_04
R315 25.5_1%_04
R344
*100K_04
Q18
2SK3018S3
G
DS
Q9
2SK3018S3
G
DS
H_PROCHOT#
CAD Note: Capacitor
need to be placed
close to buffer output pin
H_PM_SYNC[16]
H_PECI[19,29]
R345 *100K_04
Z0302
1.05VS
1.5V
1.05VS
1.5V
3.3V
1.05VS
3.3VS
XD P_ D BR _R
XD P_ TMS
XD P_ TD O_ R
PU/PD for JTAG signals
XD P_ TR ST #
XDP_PREQ#
XD P_ TD I _R
XD P_ TC LK
H_CPUPWRGD_R
Processor Pullups/Pull downs
TRACE WIDTH 10MIL, LENGTH <500MILS
DDR3 Compensation Signals
SM_RCOMP_2
SM_RCOMP_1
SM_RCOMP_0
VDDPWRGOOD_R
XD P _ TR S T #
XD P _ TC L K
XD P _ TM S
XD P _ TD I _ R
CPUDRAMRST#
H_PROCHOT#_D
H_CATERR#
Buffered reset to CPU
XD P _ TD O _ R
XDP_PREQ#
PM_SYNC_R
If PROCHOT# is not used, then it must
be terminated with a 68-£[ +-5%
pull-up resistor to 1.05VS_VTT .
Ivy/Sandy Bridge Processor 2/7
( CLK,MISC,JTAG )
H_PROCHOT#
SM_RCOMP_2
SM_RCOMP_0
SM_RCOMP_1
CPUDRAMRST#
S3 circuit:- DRAM_RST# to memory
should be high during S3
Z0303
XD P _ D B R _ R
XD P _ BP M 1 _R
XD P _ BP M 0 _R
XD P _ BP M 6 _R
XD P _ BP M 5 _R
XD P _ BP M 4 _R
XD P _ BP M 3 _R
XD P _ BP M 2 _R
XD P _ BP M 7 _R
H_PECI_R
DRAMRST_CNTRL [9,10,15]
PLT_R ST#[11,18,28]
CLK_EXP_N [15]
CLK_EXP_P [15]
H_PROCHOT_EC[29]
3.3V[2,6,11,27,28,30,31,33,34,37,38]
CLK_DP_P [15]
CLK_DP_N [15]
3.3VS[9,10,11,12,13,14,15,16,17,18,19,20,21,25,26,27,28,29,30,31,32,33,34,39]
H_CPUPWRGD[19]
1.05VS[2,5,6,14,15,16,19,20,21,35,38,39]
PM_DRAM_PWR GD[16]
1.5V[6,9,10,21,37]
RN18
*51_8P4R_04
8 1
7 2
6
5
3
4
H_CPUPWRGD_R
XD P _ PR D Y #
H_PROCHOT#[39]
H_THRMTRIP#[19]
H_SNB_IVB#[19]
DDR3_DRAMRST# [9,10]
H_THRMTRIP#_R
BUF_CPU_RST#
Normal solution
Cost down solution
R340 2K_1%_04
R335
1K_1%_04
To Next Page
Loading...
