DDC RDC-19220 Series - Page 17

17
Data Device Corporation
www.ddc-web.com
RDC-19220 SERIES
P-05/05-0
FIGURE 16B. FILTERED/BUFFERED ENCODER EMULATOR CIRCUIT
LSB +1
LSB
EL
-5 V
CB (ZI)
(ZI)
A
B
FIGURE 16A. INCREMENTAL ENCODER EMULATION
LSB +1
LSB
EL
-5 V
RDC-19220
CB/NRP
R1
2k
D1
1N4148
C1
220 pF
4
5
C2
220 pF
13
12
C3
120 pF
9
10
R2
2k
U2A
74AC86
2
1
A
B
NRP
8
6
11
3
NOTE: CMOS LOGIC IS RECOMMENDED. TTL AND TTL
COMPATIBLE LOGIC WILL SKEW THE DELAYS.
U2D
74AC86
U2B
74AC86
U2C
74AC86
R3
2k