16
Data Device Corporation
www.ddc-web.com
RDC-19220 SERIES
Q-05/05-0
Therefore, there is no need to monitor the CB line when
applying an inhibit signal to the converter.
BUILT-IN-TEST (BIT
)
The Built-ln-Test output (BIT
) monitors the level of error from the
demodulator. This signal is the difference in the input and output
angles and ideally should be zero. However, if it exceeds approx-
imately 100 LSBs (of the selected resolution) the logic level at
BIT
will change from a logic 1 to a logic 0.
This condition will occur during a large step and reset after the
converter settles out. BIT will also change to logic 0 for an over-
velocity condition, because the converter loop cannot maintain
input/output or if the converter malfunctions where it cannot
maintain the loop at a null. BIT
will also be set low for a detect-
ed total Loss-of-Signal (LOS). The BIT
signal may pulse during
certain error conditions (i.e., converter spin around or signal
amplitude on threshold of LOS).
LOS will be detected if both sin and cos input voltages are less
than 800 mV peak. The LOS has a filter on it to filter out the ref-
erence. Since the lowest specified frequency is 47hz (-27ms) the
filter must have a time constant long enough to filter this out.
Time constants of 50ms or more are possible.
ENCODER EMULATION
The RDC-19220 can be made to emulate incremental optical
encoder output signals, where such an interface is desired. This
is accomplished by tying EL
to -5 V, whereby CB becomes Zero
Index (Zl) Logic 1 at all 0s, the LSB+1 becomes A, and the exclu-
sive-or of the LSB and LSB+1 becomes B emulating A QUAD B
signals as illustrated in FIGURE 16A. Also, the LSB byte is
always enabled.
FIGURE 16B illustrates a more detailed circuit with delays and
filtering to eliminate potential glitch due to data skew and rise/fall
differences caused by logic loading.
LVDT MODE
As shown in TABLE 1 the RDC-19220 Series units can be made
to operate as LVDT-to-digital converters by connecting
Resolution Control inputs A and B to “0,” “1,” or the -5 volt sup-
ply. In this mode the RDC-19220 Series functions as a ratiomet-
ric tracking linear converter. When linear ac inputs are applied
from a LVDT the converter operates over one quarter of its
range. This results in two less bits of resolution for LVDT mode
than are provided in resolver mode.
FIGURE 12B shows a direct LVDT 2 Vrms full scale input. Some
LDVT output signals will need to be scaled to be compatible with
the converter input. FIGURE 12C is a schematic of an input scal-
ing circuit applicable to 3-wire LVDTs. The value of the scaling
constant “a” is selected to provide an input of 2 Vrms at full
stroke of the LVDT. The value of scaling constant “b” is selected
to provide an input of 1 Vrms at null of the LVDT. Suggested
components for implementing the input scaling circuit are a quad
op-amp, such as a 4741 type, and precision film resistors of
0.1% tolerance. FIGURE 12A illustrates a 2-wire LVDT configu-
ration.
Data output of the RDC-19220 Series is Binary Coded in LVDT
mode. The most negative stroke of the LVDT is represented by
all zeros and the most positive stroke of the LVDT is represent-
ed by all ones. The most significant 2 bits (2 MSBs) may be
used as overrange indicators. Positive overrange is indicated by
code “01” and negative overrange is indicated by code “11” (see
TABLE 7).
INHIBIT, ENABLE, AND CB TIMING
The Inhibit (INH) signal is used to freeze the digital output angle
in the transparent output data latch while data is being trans-
ferred. Application of an Inhibit signal does not interfere with the
continuous tracking of the converter. As shown in FIGURE 13,
angular output data is valid 300 ns maximum after the applica-
tion of the negative inhibit pulse.
Output angle data is enabled onto the tri-state data bus in two
bytes. Enable MSBs (EM
) is used for the most significant 8 bits
and Enable LSBs (EL
) is used for the least significant 8 bits. As
shown in FIGURE 14, output data is valid 150 ns maximum after
the application of a negative enable pulse. The tri-state data bus
returns to the high impedance state 100 ns maximum after the
rising edge of the enable signal.
The Converter Busy (CB) signal indicates that the tracking con-
verter output angle is changing 1 LSB. As shown in FIGURE 15,
output data is valid 50 ns maximum after the middle of the CB
pulse. CB pulse width is 1/40 Fs, which is nominally 375 ns.
Note: The converter INH
may be applied regardless of the CB
line state. If the CB is busy the converter INH
will wait for
the timing to CB “Figure 15” before setting the INH
latch.
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