Dell EMC PowerEdge MX740c - Memory Configurations; Memory RAS Features

Memory congurations
The MX740c servers support exible memory congurations ranging from capacities of 8GB (minimum) to 3TB (maximum). The
MX740c supports up to 12 DIMMs per processor (up to 24 DIMMs in a dual- processor conguration). Each server has 6 memory
channels per processor, with each channel supporting up to 2 DIMMs.
System supports a exible memory conguration, according to the following population rules:
• Speed: If DIMMs of dierent speeds are mixed, all channels across all processors operate at the slowest DIMM's common
frequency
• DIMM type: Only one type of DIMM is allowed per system: RDIMM, or LRDIMM. These types cannot be mixed.
• DIMMs with dierent data widths can be mixed. For 14G, DIMMs with x4 and x8 data widths are supported and mixing is
allowed.
• Can mix DIMMs with dierent capacities.
– Population rules require the largest capacity DIMM be placed rst (slot A1 populated rst, then A2, and so on. The second
CPU mirrors the rst CPU population).
– Maximum of two dierent capacity DIMMs allowed in a system.
• Mixing of DIMMs with dierent ranks are allowed.
– Maximum of two dierent rank DIMMs allowed in a system.
Memory RAS features
Reliability, Availability, and Serviceability (RAS) features help keep the system online and operational without signicant impact to
performance, and can decrease data loss and crashing due to errors. RAS aids in rapid, accurate diagnosis of faults which require
service.
The table below describes the memory RAS features supported on the MX740C.
Feature
Description
Dense conguration optimized prole Increased memory reliability can be a result from this selectable
platform prole that adjusts parameters to reduce faults
regarding refresh rates, speed, temperature, and voltage.
Memory demand and patrol scrubbing Demand scrubbing is the ability to write corrected data back to
the memory once a correctable error is detected on a read
transaction. Patrol scrubbing proactively searches the system
memory, repairing correctable errors.
Recovery from single DRAM device failure (SDDC) Recovery from Single DRAM Device Failure (SDDC) provides
error checking and correction that protects against any single
memory chip failure as well as multi- bit errors from any portion
of a single memory chip.
Failed DIMM isolation This feature provides the ability to identify a specic failing
DIMM channel pair, thereby enabling the user to replace only the
failed DIMM pair.
Memory mirroring Memory mirroring is a method of keeping a duplicate (secondary
or mirrored) copy of the contents of memory as a redundant
backup for use if the primary intra-socket memory fails. The
mirrored copy of the memory is stored in memory of the same
processor socket.
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