Denon AVR-550SD

12
AVR-550SD
No. Pin Name I/O Function
55 AVDD - Analog Power Supply Pin, 4.5Va5.5V
56 AVSS -
Analog Ground Pin, 0V
57 RX0 I
Receiver Channel 0 Pin (Internal biased pin)
This channel is default in serial mode.
58 NC -
No Connect
This pin should be connected to PVSS.
59 RX1 I Receiver Channel 1 Pin (Internal biased pin)
60 TEST1 I
Test 1 Pin
This pin should be connected to PVSS.
61 RX2 I Receiver Channel 2 Pin (Internal biased pin)
62 NC -
No Connect
This pin should be connected to PVSS.
63 RX3 I Receiver Channel 3 Pin (Internal biased pin)
64 PVSS - PLL Ground pin
65 R -
External Resistor Pin
12k: +/-1% resistor should be connected to PVSS externally.
66 PVDD - PLL Power supply pin, 5.0V
67 RX4 I Receiver Channel 4 Pin (Internal biased pin)
68 TEST2 I
Test 2 Pin
This pin should be connected to PVSS.
69 RX5 I Receiver Channel 5 Pin (Internal biased pin)
70 CAD0 I
Chip Address 0 Pin (ADC/DAC part)
71 RX6 I Receiver Channel 6 Pin (Internal biased pin)
72 CAD1 I
Chip Address 1 Pin (ADC/DAC part)
73 RX7 I Receiver Channel 7 Pin (Internal biased pin)
74 I2C I
Control Mode Select Pin.
“L”: 4-wire Serial, “H”: I
2
C Bus
75 DAUX2 I Auxiliary Audio Data Input Pin (DIR/DIT part)
76 VIN I V-bit Input Pin for Transmitter Output
77 MCLK I
Master Clock Input Pin
78 TX0 O Transmit Channel (Through Data) Output 0 Pin
79 TX1 O
Transmit Channel Output1 pin
When TX bit = “0”, Transmit Channel (Through Data) Output 1 Pin.
When TX bit = “1”, Transmit Channel (DAUX2 Data) Output Pin (Default).
80 INT0 O Interrupt 0 Pin