Denon DNP-800NE - Page 26

PCF8574APWR (MAIN : IC503,U504)
Terminal Function
I/O Expander (U1001, U1003, U1006), Open Drain
Addr.
Port
Port Name
ND8006 Function
name
Hardware PD/PU I/O
Nor-
mal
STBY.
Net-
work
STBY.
Detail of Function
0x38 U1001, P0 CD_OFF PU (P3V3_UCOM) 4.7kohms O O/L O/L CD Power Control
0x38 U1001, P1 OPT_POWER_OFF PU (P3V3_UCOM) 10kohms O O/L O/L S/PDIF Output Jack Power Control
0x38 U1001, P2 LED_DOUT_OFF PU (P3V3_UCOM) 10kohms O O/L O/L Digital Out OFF-mode Indicator LED Control
0x38 U1001, P3 LED_DISP_OFF PU (P3V3_UCOM) 10kohms O O/L O/L Display OFF-mode Indicator LED Control
0x38 U1001, P4 HP_GAIN_H PU (P3V3_UCOM) 10kohms O O/L O/L Headphone Amp. Gain = High
0x38 U1001, P5 HP_GAIN_M PU (P3V3_UCOM) 10kohms O O/L O/L Headphone Amp. Gain = Mid
0x38 U1001, P6 P5V_POWER_OFF PU (P3V3_UCOM) 10kohms O O/L O/L "P5V_D_AUDIO" Power Control
0x38 U1001, P7 RSV PU (P3V3_UCOM) 10kohms O O/L O/L [Unused] Line Out Gain Control (DSD/PCM)
0x39 U1003, P0 C_USBB_MCK_SEL PU (P3V3_UCOM) 10kohms O O/L O/L To CPLD, USBB MCK 24MHz(H) or 22MHz(L) Select
0x39 U1003, P1 C_CS2K_MCK_SEL PU (P3V3_UCOM) 10kohms O O/L O/L
To CPLD, CS2000-CP MCK 24MHz(H) or 22MHz(L)
Select
0x39 U1003, P2 C_CS2K_LRCK_SEL PU (P3V3_UCOM) 10kohms O O/L O/L To CPLD, CS2000-CP LRCK Control
0x39 U1003, P3
C_TDM_CONV_
RESET
PU (P3V3_UCOM) 10kohms O O/L O/L
To CPLD, TDM2PCM/DSD Converter Reset(L) or Un-
Reset(H) Control
0x39 U1003, P4 C_DIR_MCK_SEL PU (P3V3_UCOM) 10kohms O O/L O/L
To CPLD, PCM9211 ADC MCK 24MHz(H) or 22MHz(L)
Select
0x39 U1003, P5
C_PCM_DSD_
MODE
PU (P3V3_UCOM) 10kohms O O/L O/L To CPLD, Main Selector PCM(H) or DSD(L) Select
0x39 U1003, P6
C_PLD_DAC1_
MUTE
PU (P3V3_UCOM) 10kohms O O/L O/L
To CPLD, ES9016K2M Digital Mute(L) or Un-Mute(H)
Select
0x39 U1003, P7
C_DSD_PHASE_
MODE
PU (P3V3_UCOM) 10kohms O O/L O/L
To CPLD, ES9016K2M DSD Data Phase Mode(H) or
Normal Mode(L) Select
0x3A U1006, P0 C_PLD_FS0 PU (P3V3_UCOM) 10kohms O O/H O/H [Unused] To CPLD, Fs Control 0
0x3A U1006, P1 C_PLD_FS1 PU (P3V3_UCOM) 10kohms O O/H O/H [Unused] To CPLD, Fs Control 1
0x3A U1006, P2 C_DAC1_MCK_SEL PU (P3V3_UCOM) 10kohms O O/H O/H [Unused] To CPLD, ES9016K2M MCK Control
0x3A U1006, P3 C_SRC_MCK_SEL PU (P3V3_UCOM) 10kohms O O/H O/H [Unused] To CPLD, AK4137 MCK Control
0x3A U1006, P4 SRC_CM0 PU (P3V3_UCOM) 10kohms O O/H O/H [Unused] To CPLD, AK4137 Multiplication Control 0
0x3A U1006, P5 SRC_CM1 PU (P3V3_UCOM) 10kohms O O/H O/H [Unused] To CPLD, AK4137 Multiplication Control 1
0x3A U1006, P6 SRC_CM2 PU (P3V3_UCOM) 10kohms O O/H O/H [Unused] To CPLD, AK4137 Multiplication Control 2
0x3A U1006, P7 SRC_CM3 PU (P3V3_UCOM) 10kohms O O/H O/H [Unused] To CPLD, AK4137 Multiplication Control 3
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12
11
INT
SCL
NC
SDA
V
CC
A0 A1
NC
A2 P0
P7 P6 NC P5 P4
GND
P3 NC P2 P1
DGV OR PW PACKAGE
(TOP VIEW)
Pin Functions
PIN
TYPE DESCRIPTION
NAME RGY DGV or PW DW or N
Address inputs 0 through 2. Connect directly to V
CC
or ground. Pullup
A[0..2] 6, 7, 9 6, 7, 9 1, 2, 3 I
resistors are not needed.
GND 15 15 8 — Ground
INT 1 1 13 O Interrupt output. Connect to V
CC
through a pullup resistor.
NC 3, 8, 13, 18 3, 8, 13, 18 - — Do not connect
4, 5, 6, 7,
10, 11, 12, 14, 10, 11, 12, 14,
P[0..7] 9, 10, 11, I/O P-port input/output. Push-pull design structure.
16, 17, 19, 20 16, 17, 19, 20
12
SCL 2 2 14 I Serial clock line. Connect to V
CC
through a pullup resistor
SDA 4 4 15 I/O Serial data line. Connect to V
CC
through a pullup resistor.
V
CC
5 5 16 — Voltage supply
NCP380 (MAIN : U509)
Terminal Function
Block Diagram
NCP380
http://onsemi.com
2
IN OUT
EN
ILIM*
GND
NCP380
USB
Port
GND
D+
D−
VBUS
Rlim
USB INPUT
5V
EN
FLAG
USB
DATA
Rfault
*
Figure 1. Typical Application Circuit
100 k
1 F
120 F
FLAG
*For adjustable version only.
(Top view)
Figure 2. Pin Connections
1
2
3
6
5
4
OUT
ILIM*
FLAG
IN
GND
EN
PAD1
UDFN6
OUT
GND
FLAG
IN
EN
1
2
3
5
4
TSOP−5
1
2
3
6
4
OUT
ILIM*
5
FLAG
IN
GND
EN
TSOP−6
*For adjustable version only, otherwise not connected.
PIN FUNCTION DESCRIPTION
Pin Name Type Description
EN INPUT Enable input, logic low/high (i.e. EN or EN) turns on power switch
GND POWER Ground connection;
IN POWER
Power−switch input voltage; connect a 1 F or greater ceramic capacitor from IN to GND as close as
possible to the IC.
FLAG OUTPUT Active−low open−drain output, asserted during overcurrent, overtemperature or reverse−voltage
conditions. Connect a 10 k or greater resistor pull−up, otherwise leave unconnected.
OUT OUTPUT
Power−switch output; connect a 1 F ceramic capacitor from OUT to GND as close as possible to the IC
is recommended. A 1 F or greater ceramic capacitor from OUT to GND must be connected if the USB
requirement (i.e.120 F capacitor minimum) is not met.
ILIM* INPUT
External resistor used to set current−limit threshold; recommended 5 k < R
ILIM
< 250 k.
PAD1** THERMAL Exposed Thermal Pad: Must be soldered to PCB Ground plane
*(For adjustable version only, otherwise not connected.
**For DFN version only.
NCP380
http://onsemi.com
2
IN OUT
EN
ILIM*
GND
NCP380
USB
Port
GND
D+
D−
VBUS
Rlim
USB INPUT
5V
EN
FLAG
USB
DATA
Rfault
*
Figure 1. Typical Application Circuit
100 k
1 F
120 F
FLAG
*For adjustable version only.
(Top view)
Figure 2. Pin Connections
1
2
3
6
5
4
OUT
ILIM*
FLAG
IN
GND
EN
PAD1
UDFN6
OUT
GND
FLAG
IN
EN
1
2
3
5
4
TSOP−5
1
2
3
6
4
OUT
ILIM*
5
FLAG
IN
GND
EN
TSOP−6
*For adjustable version only, otherwise not connected.
PIN FUNCTION DESCRIPTION
Pin Name Type Description
EN INPUT Enable input, logic low/high (i.e. EN or EN) turns on power switch
GND POWER Ground connection;
IN POWER
Power−switch input voltage; connect a 1 F or greater ceramic capacitor from IN to GND as close as
possible to the IC.
FLAG OUTPUT Active−low open−drain output, asserted during overcurrent, overtemperature or reverse−voltage
conditions. Connect a 10 k or greater resistor pull−up, otherwise leave unconnected.
OUT OUTPUT
Power−switch output; connect a 1 F ceramic capacitor from OUT to GND as close as possible to the IC
is recommended. A 1 F or greater ceramic capacitor from OUT to GND must be connected if the USB
requirement (i.e.120 F capacitor minimum) is not met.
ILIM* INPUT
External resistor used to set current−limit threshold; recommended 5 k < R
ILIM
< 250 k.
PAD1** THERMAL Exposed Thermal Pad: Must be soldered to PCB Ground plane
*(For adjustable version only, otherwise not connected.
**For DFN version only.
NCP380
http://onsemi.com
7
BLOCK DIAGRAM
Gate Driver
UVLO
Vref
TSD
Control logic
and timer
EN block
Flag
Osc
IN
OUT
/FLAG
GND
EN
Blocking control
Current
Limiter
ILIM*
Figure 5. Block Diagram
*For adjustable version only, otherwise not connected.
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VOUT
IOCP
IOUT
Drop due to
capacitor charge
Figure 6. Heavy capacitive load
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OCP
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V
OUT
 R
LOAD
 I
OCP
(eq. 1)
Before Servicing
This Unit
Electrical Mechanical Repair Information Updating
26