52
BQ24753A_(U2) TOP View
BQ24753A_(U2) PIN FUNCTIONS-28-PIN QFN
1
FEATURES APPLICATIONS
DESCRIPTION
ACOP
bq24753A
28LDQFN
TOP VIEW
LEARN
SRN
BAT
CELLS
SRP
SRSET
IADAPT
ACDRV
ACSET
CHGEN
ACN
ACP
ACDET
PVCC
BTST
HIDRV
REGN
PH
LODRV
PGND
OVPSET
AGND
VREF
VADJ
VDAC
ACGOOD
BATDRV
1
2
3
4
5
6
7
8 9 10 11 12 13 14
15
16
17
18
19
20
21
27 26 25 24 23 22
28
bq24753A
www.ti.com
....................................................................................................................................................................................................... SLUS920– JULY 2009
Host-Controlled Li-Ion and Li-Polymer Battery Charger
with Low I
q
and System Power Selector
• Notebook, Netbook and Ultra-Mobile
2
• NMOS-NMOS Synchronous Buck Converter
Computers
with 300 kHz Frequency and >95% Efficiency
• Portable Data Capture Terminals
• 30-ns Minimum Driver Dead-time and 99.5%
• Portable Printers
Maximum Effective Duty Cycle
• Medical Diagnostics Equipment
• High-Accuracy Voltage and Current Regulation
• Battery Bay Chargers
– ±0.5% Charge Voltage Accuracy
• Battery Back-up Systems
– ±3% Charge Current Accuracy
– ±3% Adapter Current Accuracy
– ±2% Input Current Sense Amp Accuracy
The bq24753A is a high-efficiency, synchronous
• Integration
battery charger with integrated compensation and
– Automatic System Power Selection From
system power selector logic, offering low component
count for space-constrained Li-Ion and Li-Polymer
AC/DC Adapter or Battery
battery charging applications. Ratiometric charge
– Internal Loop Compensation
current and voltage programming allows for high
– Internal Soft Start
regulation accuracies, and can be either hardwired
• Safety
with resistors or programmed by the system
power-management microcontroller using a DAC or
– Programmable Input Overvoltage
GPIOs.
Protection (OVP)
The bq24753A charges two, three, or four series Li+
– Fast Dynamic Power Management (DPM)
cells, supporting up to 10 A of charge current, and is
– Programmable Inrush Adapter Power
available in a 28-pin, 5x5-mm thin QFN package.
(ACOP) and Overcurrent (ACOC) Limits
– Reverse-Conduction Protection Input FET
• Supports Two, Three, or Four Li+ Cells
• 8 – 24 V AC/DC-Adapter Operating Range
• Analog Inputs with Ratiometric Programming
via Resistors or DAC/GPIO Host Control
– Charge Voltage (4-4.512 V/cell)
– Charge Current (up to 10 A, with 10-m)
– Adapter Current Limit (DPM)
• Status and Monitoring Outputs
– Adapter Present with Programmable
Voltage Threshold
– Current Drawn from Input Source
• Battery Learn Cycle Control
• Charge Enable
• 28-pin, 5x5-mm QFN package
• Energy Star Low I
q
– < 10 µA Off-State Battery Discharge Current
– < 1.5 mA Off-State Input Quiescent Current
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
bq24753A
SLUS920–JULY 2009 .......................................................................................................................................................................................................
www.ti.com
Table 1. PIN FUNCTIONS – 28-PIN QFN
PIN
DESCRIPTION
NAME NO.
CHGEN
1 Charge enable active-low logic input. LO enables charge. HI disables charge.
Adapter current sense resistor, negative input. A 0.1-µF ceramic capacitor is placed from ACN to ACP to provide
ACN 2 differential-mode filtering. An optional 0.1-µF ceramic capacitor is placed from ACN pin to AGND for common-mode
filtering.
Adapter current sense resistor, positive input. A 0.1-µF ceramic capacitor is placed from ACN to ACP to provide
ACP 3
differential-mode filtering. A 0.1-µF ceramic capacitor is placed from ACP pin to AGND for common-mode filtering.
AC adapter to system-switch driver output. Connect directly to the gate of the ACFET P-channel power MOSFET and
the reverse conduction blocking P-channel power MOSFET. Connect both FETs as common-source. Connect the
ACFET drain to the system-load side. The PVCC should be connected to the common-source node to ensure that the
driver logic is always active when needed. If needed, an optional capacitor from gate to source of the ACFET is used to
ACDRV
4
slow down the ON and OFF times. The internal gate drive is asymmetrical, allowing a quick turn-off and slower turn-on
in addition to the internal break-before-make logic with respect to the BATDRV. The output goes into linear regulation
mode when the input sensed current exceeds the ACOC threshold. ACDRV is latched off after ACOP voltage exceeds 2
V, to protect the charging system from an ACFET-overpower condition.
Adapter detected voltage set input. Program the adapter detect threshold by connecting a resistor divider from adapter
ACDET 5 input to ACDET pin to AGND pin. Adapter voltage is detected if ACDET-pin voltage is greater than 2.4 V. The I
ADAPT
current sense amplifier is active when the ACDET pin voltage is greater than 0.6 V.
Adapter current set input. The voltage ratio of ACSET voltage versus VDAC voltage programs the input current
regulation set-point during Dynamic Power Management (DPM). Program by connecting a resistor divider from VDAC to
ACSET 6
ACSET to AGND; or by connecting the output of an external DAC to the ACSET pin and connect the DAC supply to the
VDAC pin.
Input power limit set input. Program the input overpower time constant by placing a ceramic capacitor from ACOP to
AGND. The capacitor sets the time that the input current limit, ACOC, can be sustained before exceeding the
ACOP 7
power-MOSFET power limit. When the ACOP voltage exceeds 2 V, then the ACDRV latches off to protect the charge
system from an overpower condition, ACOP. Reset latch by toggling ACDET or PVCC_UVLO.
Set input over voltage protection threshold. Charge is disabled and ACDRV is turned off if adapter input voltage is
higher than the OVPSET programmed threshold. Input overvoltage, ACOV, disables charge and ACDRV when
OVPSET 8
OVPSET > 3.1 V. ACOV does not latch. Program the overvoltage protection threshold by connecting a resistor divider
from adapter input to OVPSET pin to AGND pin.
Analog ground. Ground connection for low-current sensitive analog and digital signals. On PCB layout, connect to the
AGND 9
analog ground plane, and only connect to PGND through the PowerPad underneath the IC.
3.3-V regulated voltage output. Place a 1-µF ceramic capacitor from VREF to AGND pin close to the IC. This voltage
VREF 10 could be used for ratiometric programming of voltage and current regulation. Do not apply an external voltage source on
this pin.
Charge voltage set reference input. Connect the VREF or external DAC voltage source to the VDAC pin. Battery
voltage, charge current, and input current are programmed as a ratio of the VDAC pin voltage versus the VADJ,
VDAC 11 SRSET, and ACSET pin voltages, respectively. Place resistor dividers from VDAC to VADJ, SRSET, and ACSET pins
to AGND for programming. A DAC could be used by connecting the DAC supply to VDAC and connecting the output to
VADJ, SRSET, or ACSET.
Charge voltage set input. The voltage ratio of VADJ voltage versus VDAC voltage programs the battery voltage
regulation set-point. Program by connecting a resistor divider from VDAC to VADJ, to AGND; or, by connecting the
VADJ 12
output of an external DAC to VADJ, and connect the DAC supply to VDAC. VADJ connected to REGN programs the
default of 4.2 V per cell.
Valid adapter active-low detect logic open-drain output. Pulled low when Input voltage is above programmed ACDET.
ACGOOD
13
Connect a 10-k pullup resistor from ACGOOD to VREF, or to a different pullup-supply rail.
Battery to system switch driver output. Gate drive for the battery to system load BAT PMOS power FET to isolate the
system from the battery to prevent current flow from the system to the battery, while allowing a low impedance path
from battery to system and while discharging the battery pack to the system load. Connect this pin directly to the gate of
BATDRV
14 the input BAT P-channel power MOSFET. Connect the source of the FET to the system load voltage node. Connect the
drain of the FET to the battery pack positive node. An optional capacitor is placed from the gate to the source to slow
down the switching times. The internal gate drive is asymmetrical to allow a quick turn-off and slower turn-on, in addition
to the internal break-before-make logic with respect to ACDRV.
Adapter current sense amplifier output. IADAPT voltage is 20 times the differential voltage across ACP-ACN. Place a
IADAPT 15
100-pF or less ceramic decoupling capacitor from IADAPT to AGND.
Charge current set input. The voltage ratio of SRSET voltage versus VDAC voltage programs the charge current
SRSET 16 regulation set-point. Program by connecting a resistor divider from VDAC to SRSET to AGND; or by connecting the
output of an external DAC to SRSET pin and connect the DAC supply to VDAC pin.
Battery voltage remote sense. Directly connect a kelvin sense trace from the battery pack positive terminal to the BAT
BAT 17 pin to accurately sense the battery pack voltage. Place a 0.1-µF capacitor from BAT to AGND close to the IC to filter
high-frequency noise.
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Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s) :bq24753A
MSP430G2x32
MSP430G2x02
www.ti.com
SLAS723F –DECEMBER 2010 –REVISED MAY 2012
TERMINAL FUNCTIONS
Table 2. Terminal Functions
TERMINAL
NO.
I/O DESCRIPTION
NAME
N14, RSA1 N20,
PW14 6 PW20
P1.0/ General-purpose digital I/O pin
TA0CLK/ Timer0_A, clock signal TACLK input
2 1 2 I/O
ACLK/ ACLK signal output
A0 ADC10 analog input A0
(1)
P1.1/ General-purpose digital I/O pin
TA0.0/ 3 2 3 I/O Timer0_A, capture: CCI0A input, compare: Out0 output
A1 ADC10 analog input A1
(1)
P1.2/ General-purpose digital I/O pin
TA0.1/ 4 3 4 I/O Timer0_A, capture: CCI1A input, compare: Out1 output
A2 ADC10 analog input A2
(1)
P1.3/ General-purpose digital I/O pin
ADC10CLK/ ADC10, conversion clock output
(1)
5 4 5 I/O
A3/ ADC10 analog input A3
(1)
VREF-/VEREF ADC10 negative reference voltage
(1)
P1.4/ General-purpose digital I/O pin
TA0.2/ Timer0_A, capture: CCI2A input, compare: Out2 output
SMCLK/ SMCLK signal output
6 5 6 I/O
A4/ ADC10 analog input A4
(1)
VREF+/VEREF+/ ADC10 positive reference voltage
(1)
TCK JTAG test clock, input terminal for device programming and test
P1.5/ General-purpose digital I/O pin
TA0.0/ Timer0_A, compare: Out0 output
A5/ 7 6 7 I/O ADC10 analog input A5
(1)
SCLK/ USI: clk input in I2C mode; clk in/output in SPI mode
TMS JTAG test mode select, input terminal for device programming and test
P1.6/ General-purpose digital I/O pin
TA0.1/ Timer0_A, compare: Out1 output
A6/ ADC10 analog input A6
(1)
SDO/ 8 7 14 I/O USI: Data output in SPI mode
SCL/ USI: I2C clock in I2C mode
TDI/ JTAG test data input or test clock input during programming and test
TCLK
P1.7/ General-purpose digital I/O pin
A7/ ADC10 analog input A7
(1)
SDI/ 9 8 15 I/O USI: Data input in SPI mode
SDA/ USI: I2C data in I2C mode
TDO/TDI
(2)
JTAG test data output terminal or test data input during programming and test
P2.0 - - 8 I/O General-purpose digital I/O pin
P2.1 - - 9 I/O General-purpose digital I/O pin
P2.2 - - 10 I/O General-purpose digital I/O pin
P2.3 - - 11 I/O General-purpose digital I/O pin
(1) Available only on MSP430G2x32 devices.
(2) TDO or TDI is selected via JTAG instruction.
Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback 5
MSP430G2x32
MSP430G2x02
www.ti.com
SLAS723F –DECEMBER 2010 –REVISED MAY 2012
TERMINAL FUNCTIONS
Table 2. Terminal Functions
TERMINAL
NO.
I/O DESCRIPTION
NAME
N14, RSA1 N20,
PW14 6 PW20
P1.0/ General-purpose digital I/O pin
TA0CLK/ Timer0_A, clock signal TACLK input
2 1 2 I/O
ACLK/ ACLK signal output
A0 ADC10 analog input A0
(1)
P1.1/ General-purpose digital I/O pin
TA0.0/ 3 2 3 I/O Timer0_A, capture: CCI0A input, compare: Out0 output
A1 ADC10 analog input A1
(1)
P1.2/ General-purpose digital I/O pin
TA0.1/ 4 3 4 I/O Timer0_A, capture: CCI1A input, compare: Out1 output
A2 ADC10 analog input A2
(1)
P1.3/ General-purpose digital I/O pin
ADC10CLK/ ADC10, conversion clock output
(1)
5 4 5 I/O
A3/ ADC10 analog input A3
(1)
VREF-/VEREF ADC10 negative reference voltage
(1)
P1.4/ General-purpose digital I/O pin
TA0.2/ Timer0_A, capture: CCI2A input, compare: Out2 output
SMCLK/ SMCLK signal output
6 5 6 I/O
A4/ ADC10 analog input A4
(1)
VREF+/VEREF+/ ADC10 positive reference voltage
(1)
TCK JTAG test clock, input terminal for device programming and test
P1.5/ General-purpose digital I/O pin
TA0.0/ Timer0_A, compare: Out0 output
A5/ 7 6 7 I/O ADC10 analog input A5
(1)
SCLK/ USI: clk input in I2C mode; clk in/output in SPI mode
TMS JTAG test mode select, input terminal for device programming and test
P1.6/ General-purpose digital I/O pin
TA0.1/ Timer0_A, compare: Out1 output
A6/ ADC10 analog input A6
(1)
SDO/ 8 7 14 I/O USI: Data output in SPI mode
SCL/ USI: I2C clock in I2C mode
TDI/ JTAG test data input or test clock input during programming and test
TCLK
P1.7/ General-purpose digital I/O pin
A7/ ADC10 analog input A7
(1)
SDI/ 9 8 15 I/O USI: Data input in SPI mode
SDA/ USI: I2C data in I2C mode
TDO/TDI
(2)
JTAG test data output terminal or test data input during programming and test
P2.0 - - 8 I/O General-purpose digital I/O pin
P2.1 - - 9 I/O General-purpose digital I/O pin
P2.2 - - 10 I/O General-purpose digital I/O pin
P2.3 - - 11 I/O General-purpose digital I/O pin
(1) Available only on MSP430G2x32 devices.
(2) TDO or TDI is selected via JTAG instruction.
Copyright © 2010–2012, Texas Instruments Incorporated
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