Terminal Function
Pin
No.
Pin Name Signal Name I/O Initial Note
1 P9_4/DA1/TB4IN SO_DI O L
SOURCR DIRECT Relay Control (H/L=Source Direc/
Tone)
2 P9_3/DA0/TB3IN CD_DI O L CD DIRECT Relay Control (H/L=CD/Other)
3 P9_2/TB2IN/SOUT3 DAC_MOSI O L DAC control (PCM1795)
4 P9_1/TB1IN/SIN3 DAC_CS O H DAC control (PCM1795)
5 P9_0/TB0IN/CLK3 DAC_CLK O H DAC control (PCM1795)
6 BYTE GND I - GND
7 CNVSS CNVSS I - UPDATE
8 P8_7/XCIN LED_GREEN O H POWER LED (GREEN) control H/L = LED ON/OFF
9 P8_6/XCOUT EXT.PRE RELAY O L EXT.PRE Reley control H/L = EXT.PRE ON/OFF
10 *RESET RESET I - RESET_IN
11 XOUT XOUT O - XOUT
12 VSS GND I - GND
13 XIN XIN I - XIN
14 VCC1 VCC I - VCC
15 P8_5/*NMI NMI I - not use
16 P8_4/*INT2/ZP KEY_ON (INT) I - Interrupt
17 P8_3/*INT1 DIR1_CFLUG I H DIR control (PCM9211)
18 P8_2/*INT0 P_DOWN (P_OFF) I H P_DOWN detect
19 P8_1/TA4IN/*U SPK-OUT O H Speaker Relay On (H/L=Speaker ON/OFF)
20 P8_0/TA4OUT/U USB-B MODE O L FPGA control
21 P7_7/TA3IN SIG_TIMER O L NJU7181 Timmer Reset
22 P7_6/TA3OUT LED_STBY (STB_LED) O L STANDBY LED control (H/L=RED/off)
23 P7_5/TA2IN/*W USBB_DSD_PCM I L XMOS
24 P7_4/TA2OUT/W PROT-2 I - Voltage Abnormal Detect
25 P7_3/*CTS2/*RTS2/TA1IN/*V VOLTAGE_PROTECT I - Digital circuit VOLTAGE_PROTECT
26 P7_2/CLK2/TA1OUT/V PROT-1 I - DC Offset / Over Current Detection
27 P7_1/RXD2/SCL2/TA0IN/TB5IN (*OD) DIR1_NPCM I L DIR control (PCM9211)
28 P7_0/TXD2/SDA2/TA0OUT (*OD) NC O L not use
29 P6_7/TXD1/SDA1 TXD O for Update
30 P6_6/RXD1/SCL1 RXD I for Update
31 P6_5/CLK1 SCLK O L for debug
32 P6_4/*CTS1/*RTS1/*CTS0/CLKS1 BUSY O L for debug
33 P6_3/TXD0/SDA0 78212_DI O L FUNCTION SEL Data output (LC78212)
34 P6_2/RXD0/SCL0 78212_CE O L FUNCTION SEL CE output (LC78212)
35 P6_1/CLK0 78212_CK O L FUNCTION SEL Clock output (LC78212)
36 P6_0/*CTS0/*RTS0 M_MUTE O H Manual Mute (H/L=Mute ON/OFF)
37 P5_7/*RDY/CLKOUT MM/MC_RL O L MM/MC Relay Control (H/L=MM/MC)
38 P5_6/ALE NC O L not use
39 P5_5/*HOLD EPM O L for Update
40 P5_4/*HLDA E2P_CK O L E2P_CLK
41 P5_3/BCLK E2P_DO I L E2P_DO
42 P5_2/*RD E2P_DI O L E2P_DI
43 P5_1/*WRH/*BHE E2P_CS O L E2P_CS
44 P5_0/*WRL/*WR CE O L dor debug
45 P4_7/*CS3 M_B_DOWN I H Checking port for amp power supply off conrm
46 P4_6/*CS2 DET I -
Signal Detection input (H/L=Signal detect/No
signal)
47 P4_5/*CS1 MM/MC_DET I - MM/MC Slide Switch Detect (H/L=MM/MC)
48 P4_4/*CS0 ANA_MODE O L
"ANALOG MODE Relay On/Off
ANALOG MODE ON/OFF = L/H"
49 P4_3/A19 I2C_SCL_IN I H USBB SDA MONITOR
50 P4_2/A18 I2C_SDA_IN I H USBB SCL MONITOR
51 P4_1/A17 FPGA_VER_CONT O H FPGA control
52 P4_0/A16 PCM or DSD O L FPGA control
53 P3_7/A15 DAC_RST O H DAC control (PCM1795)
Pin
No.
Pin Name Signal Name I/O Initial Note
54 P3_6/A14 FRES O H FL Display Reset
55 P3_5/A13 SPDIF MODE O L FPGA control
56 P3_4/A12 ANA_LED O L LED control (Analog Mode LED ON/OFF = H/L)
57 P3_3/A11 SO_DI_LED O L LED control (Source Direct LED ON/OFF = H/L)
58 P3_2/A10 NC O L not use
59 P3_1/A9 DIR1_RST O H DIR control (PCM9211)
60 VCC2 Vcc I - VCC
61 P3_0/A8(/-/D7) NC O L not use
62 VSS GND I - GND
63 P2_7/AN2_7/A7(/D7/D6) DIR1_CIDO I H DIR control (PCM9211)
64 P2_6/AN2_6/A6(/D6/D5) DIR1_CK O L DIR control (PCM9211)
65 P2_5/AN2_5/A5(/D5/D4) DIR1_CE O H DIR control (PCM9211)
66 P2_4/AN2_4/A4(/D4/D3) DIR1_CODI O L DIR control (PCM9211)
67 P2_3/AN2_3/A3(/D3/D2) FS0 O L USB-DAC control
68 P2_2/AN2_2/A2(/D2/D1) FS1 O L USB-DAC control
69 P2_1/AN2_1/A1(/D1/D0) AL32_SIG_SEL O L USB-DAC control
70 P2_0/AN2_0/A0(/D0/-) AL32_EMPHA O L USB-DAC control
71 P1_7/D15/*INT5 USBB_MUTE I H USB-DAC control
72 P1_6/D14/*INT4 USBB_INT_REQ_N I H USBB_INT (DCD-SX11 102pin)
73 P1_5/D13/*INT3 REMOTE (RC5_IN) I - REMOTE IN
74 P1_4/D12 AL32_TEST3 O L FPGA control
75 P1_3/D11 AL32_TEST4 O H FPGA control
76 P1_2/D10 AL32_TEST5 O L FPGA control
77 P1_1/D9 A_MUTE O H
AMUTE (Mute for Digital input) (H/L=Mute OFF/
ON)
78 P1_0/D8 PCONT (P_ON) O H
POWER ON/STANDBY control (H/L=Power ON/
OFF)
79 P0_7/AN0_7/D7 MODE(PCM/DSD) O H MCLK select (H/L=DSD/PCM)
80 P0_6/AN0_6/D6 NC O L not use
81 P0_5/AN0_5/D5 DESTINATION_SEL I -
Auto Standby default setting H/L=Auto Standby
ON/OFF
82 P0_4/AN0_4/D4 VOL_DOWN O L Volume Down
83 P0_3/AN0_3/D3 VOL_UP O L Volume Up
84 P0_2/AN0_2/D2 NC O L not use
85 P0_1/AN0_1/D1 FCEN O H FL Display Chip select
86 P0_0/AN0_0/D0
AD32 Reset (FPGA_RE-
SERVE1)
O FPGA control
87 P10_7/AN7/*KI3 I2C_SDA I/O USB-DAC control
88 P10_6/AN6/*KI2 I2C_SCL I/O USB-DAC control
89 P10_5/AN5/*KI1 KEY1 (TACT) I - KEY1 (Front tact SW)
90 P10_4/AN4/*KI0 SEL I - Front input Selector SW (A/D input)
91 P10_3/AN3 USBB_RST O USB-DAC control
92 P10_2/AN2 USB-B_DETECT I USB-DAC VBUS detect
93 P10_1/AN1 FPGA_RESERVE2 O FPGA control
94 AVSS AVSS I - GND
95 P10_0/AN0 FPGA_RESERVE3 O FPGA control
96 VREF VREF I - VCC
97 AVCC AVCC I - VCC
98 P9_7/*ADTRG/SIN4 FPGA_RESERVE4 O FPGA control
99 P9_6/ANEX1/SOUT4 FDAT O H FL Display Data
100 P9_5/ANEX0/CLK4 FCLK O H FL Display CLK
27
Caution in
servicing
Electrical Mechanical Repair Information Updating
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