Denon S-102 - Page 49

49
S-102
ADVEE 111 P Analog power for video DAC.
ADVSS 112 G Analog ground for video DAC.
YDAC
113
O Video DAC output. Refer to description and matrix for UDAC pin 106.
YUV5 O YUV pixel 5 output data
PIXOUT5 O CCIR656 output pixel 5.
VDAC
114
O Video DAC output. Refer to description and matrix for UDAC pin 106.
YUV6 O YUV pixel 6 output data.
PIXOUT6 O CCIR656 output pixel 6.
FDAC
115
O Video DAC output. Refer to description and matrix for UDAC pin 106.
YUV7 O YUV pixel 7 output data.
PIXOUT7 O CCIR656 output pixel 7.
PCLK2XSCN
116
I/O 27-MHz video output pixel clock.
CAMIN4 I Camera YUV 4.
PIXIN4 I CCIR656 input pixel 4.
PCLKQSCN
117
O 13.5-MHz video output pixel clock.
AUX3[2] I/O Aux3 data I/O; (5V tolerant input).
CAMIN5 I Camera YUV 5.
PIXIN5 I CCIR656 input pixel 5.
VSYNC#
118
I/O Vertical sync; (5V tolerant input).
AUX3[1] I/O Aux3 data I/O; (5V tolerant input).
CAMIN6 I Camera YUV 6.
PIXIN6 I CCIR656 input pixel 6.
HSYNC#
119
I/O Horizontal sync; (5V tolerant input).
AUX3[0] I/O Aux3 data I/O; (5V tolerant input).
CAMIN7 I Camera YUV 7.
PIXIN7 I CCIR656 input pixel 7.
HD[5:0]
122-127
I/O Host data bus lines; (5V tolerant input).
DCI[5:0] I/O DVD channel data I/O; (5V tolerant input).
AUX1[5:0] I/O Aux1 data I/O; (5V tolerant input).
HD6
128
I/O Host data bus line; (5V tolerant input).
DCI6 I/O DVD channel data I/O; (5V tolerant input).
AUX1[6] I/O Aux1 data I/O; (5V tolerant input).
VFD_DOUT I VFD data output.
HD7
131
I/O Host data bus line; (5V tolerant input).
DCI7 I/O DVD channel data I/O; (5V tolerant input).
AUX1[7] I/O Aux1 data I/O; (5V tolerant input).
VFD_DIN I VFD data input.
Name Pin Numbers I/O Definition