Nexys 3™ FPGA Board Reference Manual
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1.5 Register I/O
The register I/O tab requires that a corresponding IP
block, available in the Parallel Interface reference design
(DpimRef.vhd) on the Adept page of the Digilent
website, is included and active in the FPGA. This IP block
provides an EPP-style interface, where an 8-bit address
selects a register, and data read and write buttons
transfer data to and from the selected address.
Addresses entered into the address field must match the
physical address included in the FPGA IP block.
Register I/O provides an easy way to move small
amounts of data into and out of specific registers in a
given design. This feature greatly simplifies passing
control parameters into a design, or reading low-
frequency status information out of a design.
1.6 File I/O
The File I/O tab can transfer files between the PC and
the Nexys 3 FPGA. A number of bytes (specified by the
Length value) can be streamed into a specified register
address from a file or out of a specified register address
into a file. During upload and download, the file start
location can be specified in terms of bytes.
As with the Register I/O tab, File I/O also requires
specific IP to be available in the FPGA. This IP can
include a memory controller for writing files into the on-
board Ram and Flash memories.
1.7 I/O Expand
The I/O Expand tab works with an IP block in the FPGA to provide additional simple I/O beyond the physical
devices found on the Nexys 3 board. Virtual I/O devices include a 24-LED light bar, 16 slide switches, 16 push
buttons, 8 discrete LEDs, a 32-bit register that can be sent to the FPGA, and a 32-bit register that can be read from
the FPGA.
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