Eaton XN300 - Page 299

35 Counter module XN-322-1CNT-8DIO
35.6 Memory layout
295 XN300 slice modules 02/24 MN050002EN Eaton.com
0x40F4
(READ)
–0x9xx1
SUB 01
1 SystemClock Pulse frequency (System Clock)
Pulse frequency in MHz
0x0017
0x40F5 – –
2 CounterValueSDO Counter value as acyclical access (16-bit incremental
encoder counter value)
0x0018
0x40F6 – 0x8xxA
SUB 02
1 SignalConfig
Incremental encoder configuration
register
Bit 0 -1 reserved 0x001A
Bit 2 Inverted logic for R zero-position
evaluation
Bit 3 Inverted logic for B phase evalua-
tion
Bit 5-4 Bit
n+1
Bit
n
Signal analysis
0 0 Off
0 1 X1 encoding
1 0 X2 encoding
1
1 X4 encoding
Bit 6 -7 reserved
0x40F7 – 0x6xxA
SUB 01
1 EncoderStatusSDO
Incremental encoder status
register
(acyclical access)
Bit 0 -3 reserved 0x001B
Bit 4 Zero position present
Bit 5 Zero position has been crossed;
Bit 5 will be automatically reset
after the register is read.
Bit 6-7 reserved
0x40F8 – 0x6xx4
SUB 03
2 LatchValueSDO Stored counter value as acyclical access (stored 16-bit
incremental encoder counter value)
This register contains the counter value stored by a latch
pulse. The input that triggers this action must be config-
ured accordingly.
0x001C
CAN
Object
Index
Default
CAN
Mapping
EtherCA
T Object
Index
Size
(byte)
Local I/O
description
Descri
ption
bits Sta
tus
Bit
n+1
Sta
tus
Bit
n
What the state
means
Local I/O
addresse
s