Emerson PACSystems RX3i - Figure 36: Interrupt Execution Considerations; Figure 37: Interrupt Execution Considerations

PACSystems™ RX3i and RSTi-EP CPU Reference Manual Appendix A
GFK-2222AK October 2019
Serial I/O, SNP & RTU Protocols 219
system occurs at the same time so that one of them has to wait for all others to complete
before it starts.)
The maximum response times shown below do not include the two unbounded events.
I/O Interrupt Block Performance and Sweep Impact Times
Sweep Impact Item
CPE302
CPE305
CPE310
(µs)
CPU310
(µs)
CPU315/
CPU320
(µs)
CPE010
(µs)
CPE020
(µs)
CPE030
(µs)
CPE040
(µs)
I/O interrupt sweep impact
-
94
127.8
-
309.7
335
125.6
24.0
Minimum response time
Typical response time
Maximum response time
—
151.7
175.0
302.7
326.1
327.3
346.2
392.4
396.1
434.9
334
336
359
330.6
331.5
375.1
315.2
315.5
325.7
Note that the min, typical, and max response times include a 300 µs Input card filter time.
Dropped Interrupts
When multiple interrupts are triggered during the interrupt latency period, it is possible
that interrupt blocks will only be executed one time even though the interrupt trigger has
occurred more than once. The likelihood of this occurring will increase if the system
interrupt latency has increased due to the specific configuration and use of the system.
This will not cause the CPU to miss a given interrupt; just consolidate the number of times
an interrupt block is executed even though the interrupt stimulus had occurred more
than one time.
Figure 36: Interrupt Execution Considerations
94
Performance data not available for this release.