FATEK FBs-4A2D - Page 147

Basic Function Instruction
6 - 22
FUN 7 D
UDCTR
UP/DOWN COUNTER
(16-bit or 32-bit up/down 2-phase Counter)
FUN 7 D
UDCTR
Ladder Diagram Key Operations Mnemonic Codes
X18
X16
7.UDCTR
CV :
PV :
CK
U/D
CLR
R
0
CUP
X17
-
Y0
3
ORG
OUT
LD
LD
ORG X 18
LD X 17
LD X 16
FUN 7
CV： R 0
PV： − 3
FO 0
OUT Y 0
X16
X17
X18
R0
Y0
Up(add)
Down(subtract)
0
1
2
3
2
1
0
-1
-2
-3
-4
Remark 1: Since the counting operation of UDCTR is implemented by software scanning, therefore if the clock
speed is faster than the scan speed, lose count may then happen (generally the clock should not
exceed 20Hz depending on the size of the program). Please use the software or hardware high-speed
counter in the PLC. Refer to the “High Speed Counter Application” in the Advanced Manual.
Remark 2: In order to ensure the proper counting, the sustain time of the status of clock input should greater than
1 scan time.