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FATEK FBs-CB2 User Manual

FATEK FBs-CB2
348 pages
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Hardware
Contents
Chapter 1Introduction of FATEK FBS Series PLC
1.1 Appearance of Main Unit...............................................................................................................H1-1
1.2 Appearance of Expander/Module.................................................................................................H1-2
1.3 Appearance of Communication Expansion Module ....................................................................H1-4
1.4 List of FBS-PLC Models ................................................................................................................H1-5
1.5 Specifications of Main Unit ............................................................................................................H1-7
1.6 Environmental Specifications ........................................................................................................H1-8
1.7 Connection Diagrams of Various Models.....................................................................................H1-9
1.7.1 NC Control Main Unit..............................................................................................................H1-9
1.7.2 Basic/Advanced Main Unit .....................................................................................................H1-10
1.7.3 Digital I/O Expander................................................................................................................H1-12
1.7.4 Digital I/O Expansion Module.................................................................................................H1-13
1.7.5 High-Density Digital I/O Expansion Module ..........................................................................H1-14
1.7.6 Numeric I/O Expansion Module.............................................................................................H1-14
1.7.7 Analog I/O Expansion Module ...............................................................................................H1-14
1.7.8 Temperature Input Module.....................................................................................................H1-15
1.7.9 Expansion Power....................................................................................................................H1-15
1.7.10 Communication Module (CM)..............................................................................................H1-16
1.7.11 Communication Board (CB).................................................................................................H1-17
1.8 Drawings with External Dimensions .............................................................................................H1-18
Chapter 2System Architecture
2.1 Single-Unit System of FBS-PLC...................................................................................................H2-1
2.2 Formation of Multiple Units............................................................................................................H2-2
2.2.1 Connection of multiple FBS-PLC...........................................................................................H2-2
2.2.2 Connection of FBS-PLC with host computer or intelligent peripherals................................H2-3
Chapter 3Expansion of FBS-PLC
3.1 I/O Expansion.................................................................................................................................H3-1

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FATEK FBs-CB2 Specifications

General IconGeneral
BrandFATEK
ModelFBs-CB2
CategoryController
LanguageEnglish

Summary

Chapter 1: Introduction of FATEK FBS Series PLC

1.1 Appearance of Main Unit

Describes the physical structure and case sizes of FBS-PLC Main Units.

1.5 Specifications of Main Unit

Details specifications like execution speed, program memory, command types, and register allocations.

Chapter 2: System Architecture

2.1 Single-Unit System of FBS-PLC

Explains the block diagram of a Single-Unit system of FBs-PLC, including main units and I/O resources.

2.2.2 Connection FBs-PLC with Host Computer or Intelligent Peripherals

Explains connecting FBs-PLC to upper-level computers or peripherals using FATEK or Modbus protocols.

Chapter 3: Expansion of FBS-PLC

3.1 I/O Expansion

Covers Digital I/O (DI/O) and Numeric I/O (NI/O) expansion using expansion units or modules.

Chapter 4: Installation Guide

4.1 Installation Environment

Lists environmental specifications that FBS-PLC cannot exceed, including operating temperature and humidity.

4.3 Fixation by DIN RAIL

Explains the DIN RAIL mounting method for PLC fixation, including mounting and dismounting procedures.

Chapter 5: Power Supply Wiring, Power Consumption Calculation, and Power Sequence Requirements

5.1 Specifications of AC Power Sourced Power Supply and Wiring

Lists specifications for available AC power supplies (POW-14, POW-24, FBS-EPOW) and their wiring.

5.2 Specifications of DC Power Sourced Power Supply and Wiring

Details specifications for DC power sourced power supplies (POW-10-D, POW-16-D, FBS-EPOW-D) and their wiring.

5.3 Residual Capacity of Main/Expansion Unit & Current Consumption of Expansion Module

Explains residual capacity of power supplies and current consumption of expansion modules to avoid overload.

5.4 Requirement of Power Sequence in Main Unit & Expansion Unit/Module

Addresses the power-on sequence requirement for main units and expansion modules, including delay settings.

Chapter 6: Digital Input (DI) Circuit

6.1 Specifications of Digital Input (DI) Circuit

Details specifications for 5VDC differential input and 24VDC single-end input circuits, including speeds and current.

6.3 24VDC Single-End Input Circuit and Wiring for SINK/SRCE input

Covers 24VDC single-end input circuits and wiring for SINK/SRCE input, detailing response speeds and terminal usage.

Chapter 7: Digital Output (DO) Circuit

7.1 Specifications of Digital Output Circuits

Provides detailed specifications for differential, single-end transistor, relay, and TRIAC outputs.

7.5 Output Device Protection and Noise Suppression in DO Circuit

Discusses protection and noise suppression for digital output circuits, especially relays and transistors.

Chapter 8: Test Run, Monitoring and Maintenance

8.1 Inspection after Wiring and Before First Time Power on

Provides a checklist for inspection before powering on the PLC, covering power, wiring, and output circuits.

8.2 Test Run and Monitoring

Explains the Disable/Enable I/O feature for simulating inputs/outputs and monitoring PLC operation.

8.3 LED Indicators on PLC Main Unit and Troubleshooting

Describes the function of PLC main unit LED indicators (POW, RUN, ERR, RX, TX, Xn, Yn) and common troubleshooting steps.

Chapter 1: PLC Ladder Diagram and the Coding Rules of Mnemonic

1.1 The Operation Principle of Ladder Diagram

Introduces the basic principles of ladder diagrams, including elements like contacts, coils, and logic types.

Chapter 2: FBs-PLC Memory Allocation

2.1 FBs-PLC Memory Allocation

Illustrates the memory buffer organization in FBs-PLC, including SRAM and FBS-PACK memory structures.

2.2 Digital and Register Allocations

Details the allocation of digital (bit) status and register (word) data, including types, ranges, and remarks.

2.3 Special Relay Details

Explains special relays like emergency stop control, external output control, and master control selection.

2.4 Special Registers Details

Details special registers used for PID temperature control, including PWM period and error detection.

Chapter 3: FBs-PLC Instruction Lists

3.1 Sequential Instructions

Lists sequential instructions with operands, symbols, function descriptions, execution time, and instruction types.

Chapter 4: Sequential Instructions

4.1 Valid Operand of Sequential Instructions

Lists valid operands (X, Y, M, SM, S, T, C, TR, OPEN, SHORT) for sequential instructions and their ranges.

Chapter 5: Descriptions of Function Instructions

5.1 The Format of Function Instructions

Introduces the structure of function instructions, divided into input control, instruction number, operand, and output.

5.2 Use Index Register(XR) for Indirect Addressing

Discusses combining operands with pointer registers (V, Z, P0~P9) for indirect addressing, particularly with Rxxxx registers.

Chapter 6: Basic Function Instruction

T TIMER

Details the TIMER instruction (T nnn), its time bases (0.01S, 0.1S, 1S), and operand usage (Tn, PV).

T TIMER

Explains the operation of the TIMER instruction, including control inputs (EN, TIM), outputs (TUP, NUP), and preset value adjustments.

C COUNTER

Details the COUNTER instruction (C nnn), including 16-bit and 32-bit counters, preset value ranges, and descriptions of counting behavior.

C COUNTER

Illustrates examples of 16-bit fixed counters and 32-bit counters with variable preset values using registers.

SET

Explains the SET instruction for setting coils or register bits to 1, with operand details and examples of single coil and register set operations.

RESET

Details the RESET instruction for resetting coils or registers to 0, including operand details and examples for single coil and 16-bit register reset.

MC MATER CONTROL LOOP START

Explains the MC instruction for starting a master control loop, its correspondence with MCE, and active loop area behavior.

SKP SKIP START

Explains the SKP instruction for starting a skip loop, its correspondence with SKPE, and behavior based on the skip control input.

UDCTR UP/DOWN COUNTER

Details the UDCTR instruction for 16-bit or 32-bit up/down counters, including control inputs and counting behavior.

ADDITION

Covers the ADDITION instruction for performing addition of Sa and Sb, storing results in D, and setting FO flags for carry and borrow.

SUBTRACTION

Explains the SUBTRACTION instruction for subtracting Sb from Sa, storing results in D, and setting FO flags for carry and borrow.

DIVISION

Covers the DIVISION instruction for dividing Sa by Sb, storing quotient in D, and setting FO flags for zero quotient and divisor error.

COMPARE

Covers the COMPARE instruction for comparing Sa and Sb, setting FO0, FO1, FO2 based on equality, greater than, or less than conditions.

Chapter 7: Advanced Function Instructions

BREAK FROM FOR AND NEXT LOOP (BREAK)

Explains the BREAK instruction to terminate FOR and NEXT loops, its location within the loop, and program execution flow.

GENERAL PURPOSE PID OPERATION (FUN 30 PID)

Covers the PID instruction for process control, including PID formula, parameters like Kc, Ti, Td, and output control methods.

CRC16 CALCULATION (FUN31 CRC16)

Explains the CRC16 instruction for calculating and checking Cyclic Redundancy Check values for message frames, used in Modbus RTU.

ZONE COMPARE (FUN 37 ZNCMP)

Covers the ZNCMP instruction for comparing S with upper (SU) and lower (SL) limits, setting flags for inside zone, higher than upper, or lower than lower limit.

BIT READ (FUN 40 BITRD)

Explains the BITRD instruction to read the Nth bit of S data and output it to OTB, with controls for state retention.

BIT WRITE (FUN 41 BITWR)

Details the BITWR instruction to write a bit from INB into a specified bit position in matrix Md, with controls for write operation and error handling.

7-SEGMENT CONVERSION (FUN 59 →7SG)

Covers the →7SG instruction to convert alphanumeric characters to 7-segment display patterns or substituting BCD with blank code.

HOUR:MINUTE:SECOND TO SECONDS CONVERSION (FUN61 →SEC)

Details the →SEC instruction to convert time data (hours, minutes, seconds) into total seconds, storing results in D~D+1.

SECOND→HOUR:MINUTE:SECOND (FUN62 →HMS)

Covers the →HMS instruction to convert second data into hour, minute, second time values, storing results in D~D+2.

LABEL (FUN 65 LBL)

Covers the LBL instruction for marking addresses within a program to provide targets for JMP, CALL, and interrupt service.

CALL (FUN 67 CALL)

Explains the CALL instruction to execute subroutines, which must end with RTS, and the concept of nested subroutines.

FOR (FUN 70 FOR)

Explains the FOR instruction for creating program loops, its use with NEXT, nested loop structures, and range limitations.

IMMIDIATE I/O (FUN 74 IMDIO)

Covers the IMDIO instruction for immediate refresh of input/output signals, bypassing scan cycle delays, and its I/O point limitations.

DECIMAL- KEY INPUT (FUN 76 TKEY)

Explains the TKEY instruction for entering decimal numbers via input points, storing them in D, and its key-in status recording.

HEX-KEY INPUT (FUN 77 HKEY)

Details the HKEY instruction for multiplexing 16 key inputs (numeric and function keys), storing results in D, and its output requirements.

7-SEGMENT OUTPUT WITH LATCH (FUN 79 7SGDL)

Explains the 7SGDL instruction for displaying BCD data on 7-segment displays, coordinating PLC output polarity with display input.

PULSE OUTPUT (FUN 81 PLSO)

Explains the PLSO instruction for controlling pulse output (step motors), including output modes, frequency, pulse count, and direction control.

PULSE OUTPUT (FUN 81 PLSO)

Illustrates PLSO instruction usage for controlling stepping motors with forward/reverse pulses, speed, and pulse counts.

SPEED DETECTION (FUN 83 SPD)

Details the SPD instruction for detecting input signal frequency using high-speed input points and calculating revolution speed.

PATTERN CONVERSION FOR 16/7-SEGMENT DISPLAY (FUN 84 TDSP)

Covers the TDSP instruction for converting alphanumeric characters to 7-segment display patterns or substituting BCD with blank code.

PID TEMPERATURE CONTROL INSTRUCTION (FUN 86 TPCTL)

Covers the PID instruction for temperature control, including PID formula, parameters like Kc, Ti, Td, and output control methods.

PID TEMPERATURE CONTROL INSTRUCTION (FUN 86 TPCTL)

Provides PID parameter adjustment guidance (Kc, Ti, Td), default values, and notes on execution control and error handling.

CUMULATIVE TIMER (FUN87/FUN88/FUN89)

Details cumulative timer instructions (T0~T255) with ON delay and OFF delay energizing/de-energizing behaviors.

WATCHDOG TIMER (FUN 90 WDT)

Explains the WDT instruction for setting watchdog time, its safety function, and default time value.

RESET WATCHDOG TIMER (FUN 91 RSWDT)

Covers the RSWDT instruction for resetting the watchdog timer, its operation principles, and its use to trigger WDT.

HARDWARE HIGH SPEED COUNTER CURRENT VALUE (CV) ACCESS (FUN 92 HSCTR)

Details the HSCTR instruction for accessing CV values of High Speed Counters (HSC0-HSC3) and HSTA from ASIC registers.

HARDWARE HIGH SPEED COUNTER CURRENT VALUE AND PRESET VALUE WRITING (FUN 93 HSCTW)

Explains the HSCTW instruction for writing CV or PV values to HSCs and HSTA, including clearing values and interrupt execution.

ASCII WRITE (FUN 94 ASCWR)

Covers the ASCWR instruction for transmitting ASCII data to communication port 1, with output modes, control inputs, and error handling.

RAMP FUNCTION FOR D/A OUTPUT (FUN 95 RAMP)

Details the RAMP instruction for controlling D/A output, specifying timer, preset value, limits, and ramping direction.

RAMP FUNCTION FOR D/A OUTPUT (FUN 95 RAMP)

Provides program examples for RAMP function with constant and variable preset values, and explains output waveform behavior.

Table Instructions

Lists Table Instructions including data move, fill, shift, rotate, queue, stack, compare, sort, and their functionalities.

REGISTER TO TABLE SEARCH (FUN105 R-T_S)

Covers the R-T_S instruction for searching a table for data matching or differing from a source register, using a pointer.

QUEUE (FUN110 QUEUE)

Details the QUEUE instruction for FIFO data management, including push/pop operations, pointer usage, and queue empty/full flags.

STACK (FUN111 STACK)

Explains the STACK instruction for LIFO data management, similar to queue but with last-in first-out behavior, including pointer usage and status flags.

BLOCK COMPARE (FUN112 BKCMP)

Covers the BKCMP instruction for comparing blocks of data or registers against upper/lower limits, setting flags for match or mismatch.

MCMP MATRIX COMPARE (FUN125 MCMP)

Covers the MCMP instruction for comparing pairs of bits between matrixes Ma and Mb, setting flags for match, different values, or end of search.

MBRD MATRIX BIT READ (FUN126 MBRD)

Details the MBRD instruction to read bit status from a matrix Ms and output it to OTB, managing pointer increment and read-to-end flags.

MBWR MATRIX BIT WRITE (FUN127 MBWR)

Explains the MBWR instruction to write a bit from INB into a specified bit position in matrix Md, managing pointer increment and write-to-end flags.

HIGH SPEED PULSE WIDTH MODULATION OUTPUT (FUN 139 HSPWM)

Covers the HSPWM instruction for generating PWM output, specifying output mode, frequency, pulse width, and output polarity.

HIGH SPEED PULSE OUTPUT INSTRUCTION (FUN140 HSPSO)

Details the HSPSO instruction for NC positioning control, allowing programming of 250 steps, and managing pulse output modes and parameters.

NC POSITIONING PARAMETER VALUE SETTING (FUN141 MPARA)

Explains the MPARA instruction for setting NC positioning parameters dynamically, used in conjunction with FUN140.

MODBUS MASTER INSTRUCTION (FUN150 M-BUS)

Details the M-BUS instruction for PLC to act as Modbus master, communicating with peripherals via RS-485 and supporting up to 247 slave stations.

Chapter 8: Step Instruction Description

8.1 The Operation Principle of Step Ladder Diagram

Introduces step ladder diagrams, their basic unit (step), and how steps form machines or sequential controls.

8.3 Introduction of Step Instructions: STP, FROM, TO and STPEND

Introduces initial step instruction (STP), FROM, TO, and STPEND instructions for process control and program flow.

Appendix: FB-DAP Simple Human Machine Interface

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