FATEK FBs-CB2 - AND LOGICAL AND

Basic Function Instruction
6-35
FUN 18 D P
AND
LOGICAL AND
FUN 18 D P
AND
Operand
Sa: The register to be ANDed
Sb: The register to be ANDed
D : The register to store the result of AND
The Sa, Sb, D may combine with V, Z, P0~P9 to
serve indirect addressing application
WX WY WM WS TMR CTR HR IR OR HR HSCR RTCR SR ROR DR K
Range
Ope-
rand
WX0
∣
WX240
WY0
∣
WY240
WM0
∣
WM1896
WS0
∣
WS984
T0
∣
T255
C0
∣
C255
R0
∣
R3839
R3804
∣
R3903
R3904
∣
R3919
R3920
∣
R4047
R4096
∣
R4127
R4128
∣
R4135
R4136
∣
R4167
R5000
∣
R8071
D0
∣
D4095
16/32 bit
+/-number
Sa ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Sb ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
D ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○* ○* ○
● Performs logical AND operation for the data of Sa and Sb when the operation control input "EN" =1 or "EN↑"
( P instruction) from 0 to 1. This operation compares the corresponding bits of Sa and Sb (B0~B15 or
B0~B31). The bit in the D is set to 1 if both of the corresponding bits data of Sa and Sb is 1. The bit in the D is
set to 0 if one of the corresponding bits is 0.
Example Operation of 16-bit logical AND
Ladder diagram Key operations Mnemonic code
Sa :
Sb :
D :
R
R
R
1
2
D=0
18P.AND
EN
X0
0
ORG
ORG X 0
FUN 18P
Sa : R 0
Sb : R 1
D : R 2
B15 B0
↓ ↓
Sa R0 1 0 11101101101101
Sb R1 1 1 10111010100110
Ø
X0＝
B15 B0
↓ ↓
D
R2 1 0 10101000100100