FATEK FBs-CB2 - HARDWARE HIGH SPEED COUNTER CURRENT VALUE (CV) ACCESS (FUN 92 HSCTR)

Advanced Function Instruction
7-77
FUN 92 P
HSCTR
HARDWARE HIGH SPEED COUNTER CURRENT VALUE (CV) ACCESS
FUN 92 P
HSCTR
CN : Hardware high speed counter number
0: SC0 or HST0
1: SC1 or HST1
2: SC2 or HST2
3: SC3 or HST3
4: STA
z The HSC0～HSC3 counters of FBs-PLC are 4 sets of 32bit high speed counter with the variety counting
modes such as up/down pulse, pulse-direction, AB-phase. All the 4 high speed counters are built in the ASIC
hardware and could perform count, compare, and send interrupt independently without the intervention of the
CPU. In contrast to the software high speed counters HSC4～HSC7, which employ interrupt method to
request for CPU processing, hence if there are many counting signals or the counting frequency is high, the
PLC performance (scanning speed) will be degraded dramatically. Since the current values CV of HSC0～
HSC3 are built in the internal hardware circuits of ASIC, the user control program (ladder diagram) cannot
retrieve them directly from ASIC. Therefore, it must employ this instruction to get the CV value from hardware
HSC and put it into the register which control program can access. The following is the arrangement of CV,
PV in ASIC and their corresponding CV, PV registers of PLC for HSC0~HSC3.
PLC register ASIC
DR4096 CV
CV register H L
HSC0 DR4098 PV HSC0
PV register H L
DR4100 CV
CV register H L
HSC1 DR4102 PV HSC1
PV register H L
DR4104 CV
CV register H L
HSC2 DR4106 PV HSC2
PV register H L
DR4108 CV
CV register H L
HSC3 DR4110 PV HSC3
PV register H L
DR4152 CV
CV register H L
HSTA R4154 PV HSTA
PV register
z When access control “EN” =1 or “EN↑” ( P instruction) changes from 0→1, will gets the CV value of HSC
designated by CN from ASIC and puts into the HSC corresponding CV register (i.e. the CV of HSC0 will be
read and put into DR4096 or the CV of HSC1 will be read and put into DR4100).
z Although the PV within ASIC has a corresponding PV register in CPU, but it is not necessary to access it
(actually it can’t be) for that the PV value within ASIC comes from the PV register in CPU.
z HSTA is a timer, which use 0.1ms as its time base. The content of CV represents elapse time counting at
0.1mS tick.
z For detailed applications, please refer to Chapter 10 “The high speed counter and high speed timer of
FBs-PLC”.